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1 tms320dm6433 digital media processor 1.1 features tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 ? 256k-bit (32k-byte) l1p program high-performance digital media processor ram/cache [flexible allocation] (dm6433) ? 640k-bit (80k-byte) l1d data ram/cache ? 2.5-, 2-, 1.67-, 1.51-, 1.43-ns ns instruction [flexible allocation] cycle time ? 1m-bit (128k-byte) l2 unified mapped ? 400-, 500, -600-, 660-, 700-mhz c64x+? ram/cache [flexible allocation] clock rate supports little endian mode only ? eight 32-bit c64x+ instructions/cycle ? 3200, 4000, 4800, 5280, 5600 mips video processing subsystem (vpss) ? fully software-compatible with c64x ? front end provides (resizer only): ? commercial and automotive (q or s suffix) resize images from 1/4x to 4x grades separate horizontal and vertical control ? low-power device (l suffix) ? back end provides: velociti.2? extensions to velociti? hardware on-screen display (osd) advanced very-long-instruction-word (vliw) four 54-mhz dacs for a combination of tms320c64x+? dsp core ? composite ntsc/pal video ? eight highly independent functional units ? luma/chroma separate video with velociti.2 extensions: (s-video) six alus (32-/40-bit), each supports ? component (ypbpr or rgb) video single 32-bit, dual 16-bit, or quad 8-bit (progressive) arithmetic per clock cycle digital output two multipliers support four 16 x 16-bit ? 8-/16-bit yuv or up to 24-bit rgb multiplies (32-bit results) per clock ? hd resolution cycle or eight 8 x 8-bit multiplies (16-bit ? up to 2 video windows results) per clock cycle external memory interfaces (emifs) ? load-store architecture with non-aligned support ? 32-bit ddr2 sdram memory controller with 256m-byte address space (1.8-v i/o) ? 64 32-bit general-purpose registers supports up to 333-mhz (data rate) bus ? instruction packing reduces code size and interfaces to ddr2-400 sdram ? all instructions conditional ? asynchronous 8-bit wide emif (emifa) ? additional c64x+? enhancements with up to 64m-byte address reach protected mode operation flash memory interfaces exceptions support for error detection ? nor (8-bit-wide data) and program redirection ? nand (8-bit-wide data) hardware support for modulo loop auto-focus module operation enhanced direct-memory-access (edma) controller (64 independent channels) c64x+ instruction set features two 64-bit general-purpose timers (each ? byte-addressable (8-/16-/32-/64-bit data) configurable as two 32-bit timers) ? 8-bit overflow protection ? bit-field extract, set, clear one 64-bit watch dog timer ? normalization, saturation, bit-counting one uart with rts and cts flow control ? velociti.2 increased orthogonality master/slave inter-integrated circuit (i 2 c ? c64x+ extensions bus?) compact 16-bit instructions one multichannel buffered serial port additional instructions to support (mcbsp0) complex multiplies ? i2s and tdm c64x+ l1/l2 memory architecture ? ac97 audio codec interface please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this document. all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2006?2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
1.2 description tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com ? spi flexible pll clock generators ? standard voice codec interface (aic12) ieee-1149.1 (jtag?) ? telecom interfaces ? st-bus, h-100 boundary-scan-compatible ? 128 channel mode up to 111 general-purpose i/o (gpio) pins multichannel audio serial port (mcasp0) (multiplexed with other device functions) ? four serializers and spdif (dit) mode packages: 16-bit host-port interface (hpi) ? 361-pin pb-free pbga package (zwt suffix), 0.8-mm ball pitch 32-bit 33-mhz, 3.3-v peripheral component ? 376-pin plastic bga package interconnect (pci) master/slave interface (zdu suffix), 1.0-mm ball pitch 10/100 mb/s ethernet mac (emac) 0.09- m m/6-level cu metal process (cmos) ? ieee 802.3 compliant 3.3-v and 1.8-v i/o, 1.2-v internal ? supports media independent interface (mii) (-7/-6/-5/-4/-l/-q6/-q5/-q4) ? management data i/o (mdio) module 3.3-v and 1.8-v i/o, 1.05-v internal vlynq? interface (fpga interface) (-7/-6/-5/-4/-l/-q5) three pulse width modulator (pwm) outputs applications: on-chip rom bootloader ? digital media individual power-savings modes ? networked media decode the tms320c64x+? dsps (including the tms320dm6433 device) are the highest-performance fixed-point dsp generation in the tms320c6000? dsp platform. the dm6433 device is based on the third-generation high-performance, advanced velociti? very-long-instruction-word (vliw) architecture developed by texas instruments (ti), making these dsps an excellent choice for digital media applications. the c64x+? devices are upward code-compatible from previous devices that are part of the c6000? dsp platform. the c64x? dsps support added functionality and have an expanded instruction set from previous devices. any reference to the c64x dsp or c64x cpu also applies, unless otherwise noted, to the c64x+ dsp and c64x+ cpu, respectively. with performance of up to 5600 million instructions per second (mips) at a clock rate of 700 mhz, the c64x+ core offers solutions to high-performance dsp programming challenges. the dsp core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. the c64x+ dsp core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic logic units (alus). the eight functional units include instructions to accelerate the performance in video and imaging applications. the dsp core can produce four 16-bit multiply-accumulates (macs) per cycle for a total of 2800 million macs per second (mmacs), or eight 8-bit macs per cycle for a total of 5600 mmacs. for more details on the c64x+ dsp, see the tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732 ). the dm6433 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other c6000 dsp platform devices. the dm6433 core uses a two-level cache-based architecture. the level 1 program memory/cache (l1p) consists of a 256k-bit memory space that can be configured as mapped memory or direct mapped cache, and the level 1 data (l1d) consists of a 640k-bit memory space ?384k-bit of which is mapped memory and 256k-bit of which can be configured as mapped memory or 2-way set-associative cache. the level 2 memory/cache (l2) consists of a 1m-bit memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or combinations of the two. tms320dm6433 digital media processor 2 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the peripheral set includes: 1 configurable video port; a 10/100 mb/s ethernet mac (emac) with a management data input/output (mdio) module; a 4-bit transmit, 4-bit receive vlynq interface; an inter-integrated circuit (i2c) bus interface; a multichannel buffered serial port (mcbsp0); a multichannel audio serial port (mcasp0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (hpi); up to 111-pins of general-purpose input/output (gpio) with programmable interrupt/event generation modes, multiplexed with other peripherals; a uart with hardware handshaking support; 3 pulse width modulator (pwm) peripherals; 1 peripheral component interconnect (pci) [33 mhz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (emifa) for slower memories/peripherals, and a higher speed synchronous memory interface for ddr2. the dm6433 device includes a video processing subsystem (vpss) with a video processing back-end (vpbe) output. the video processing back-end (vpbe) is comprised of an on-screen display engine (osd) and a video encoder (venc). the osd engine is capable of handling 2 separate video windows and 2 separate osd windows. other configurations include 2 video windows, 1 osd window, and 1 attribute window allowing up to 8 levels of alpha blending. the venc provides four analog dacs that run at 54 mhz, providing a means for composite ntsc/pal video, s-video, and/or component video output. the venc also provides up to 24 bits of digital output to interface to rgb888 devices. the digital output is capable of 8/16-bit bt.656 output and/or ccir.601 with separate horizontal and vertical syncs. the resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/n, where n is between 64 and 1024. the ethernet media access controller (emac) provides an efficient interface between the dm6433 and the network. the dm6433 emac support both 10base-t and 100base-tx, or 10 mbits/second (mbps) and 100 mbps in either half- or full-duplex mode, with hardware flow control and quality of service (qos) support. the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the i2c and vlynq ports allow dm6433 to easily control peripheral devices and/or communicate with host processors. the rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. for details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. the dm6433 has a complete set of development tools. these include c compilers, a dsp assembly optimizer to simplify programming and scheduling, and a windows? debugger interface for visibility into source code execution. submit documentation feedback tms320dm6433 digital media processor 3
1.3 functional block diagram tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 1-1 shows the functional block diagram of the dm6433 device. figure 1-1. tms320dm6433 functional block diagram 4 tms320dm6433 digital media processor submit documentation feedback jt ag interface system control plls/clock generator input clock(s) power/sleep controller pin multiplexing dsp subsystem c64x+ dsp cpu 32 kb l1 pgm 128 kb l2 ram 80 kb l1 data video processing subsystem (vpss) 10b dac on-screen display (osd) video encoder (venc) 10b dac 10b dac10b dac back end 8b bt .656, y/c,24b rgb ntsc/ pal, s-video, rgb, ypbpr switched central resource (scr) peripherals edma i 2 c uart serial interfaces ddr2 mem ctlr (32b) async emif/ nand/ (8b) program/data storage watchdog timer pwm system general- purpose timer pci (33 mhz) vlynq emac with mdio connectivity hpi mcasp mcbsp osc boot rom gpio front end resizer
contents tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 1 tms320dm6433 digital media processor ........... 1 temperature (unless otherwise noted) ........... 141 1.1 features .............................................. 1 6 peripheral information and electrical specifications ......................................... 143 1.2 description ............................................ 2 6.1 parameter information ............................. 143 1.3 functional block diagram ............................ 4 6.2 recommended clock and control signal transition revision history ............................................... 6 behavior ............................................ 144 2 device overview ......................................... 6 6.3 power supplies .................................... 144 2.1 device characteristics ................................ 6 6.4 enhanced direct memory access (edma3) 2.2 cpu (dsp core) description ......................... 8 controller ........................................... 153 2.3 c64x+ cpu .......................................... 11 6.5 reset ............................................... 165 2.4 memory map summary ............................. 12 6.6 external clock input from mxi/clkin pin ........ 174 2.5 pin assignments .................................... 16 6.7 clock plls ......................................... 176 2.6 terminal functions .................................. 24 6.8 interrupts ........................................... 182 2.7 device support ...................................... 66 6.9 external memory interface (emif) ................. 185 2.8 device and development-support tool 6.10 video processing sub-system (vpss) overview . 194 nomenclature ....................................... 66 6.11 universal asynchronous receiver/transmitter 2.9 documentation support ............................. 68 (uart) ............................................. 208 3 device configurations ................................. 69 6.12 inter-integrated circuit (i2c) ....................... 210 3.1 system module registers ........................... 69 6.13 host-port interface (hpi) peripheral ............... 214 3.2 power considerations ............................... 70 6.14 multichannel buffered serial port (mcbsp) ........ 219 3.3 clock considerations ................................ 72 6.15 multichannel audio serial port (mcasp0) peripheral .......................................... 228 3.4 boot sequence ...................................... 75 6.16 ethernet media access controller (emac) ........ 236 3.5 configurations at reset ............................. 87 6.17 management data input/output (mdio) .......... 243 3.6 configurations after reset .......................... 90 6.18 timers .............................................. 244 3.7 multiplexed pin configurations ...................... 94 6.19 peripheral component interconnect (pci) ......... 247 3.8 device initialization sequence after reset ........ 133 6.20 pulse width modulator (pwm) ..................... 253 3.9 debugging considerations ......................... 135 6.21 vlynq ............................................. 255 4 system interconnect ................................. 137 6.22 general-purpose input/output (gpio) ............. 259 4.1 system interconnect block diagram ............... 137 6.23 ieee 1149.1 jtag ................................. 263 5 device operating conditions ....................... 139 5.1 absolute maximum ratings over operating 7 mechanical data ....................................... 265 temperature range (unless otherwise noted) ... 139 7.1 thermal data for zwt ............................. 265 5.2 recommended operating conditions ............. 140 7.1.1 thermal data for zdu ............................. 266 5.3 electrical characteristics over recommended 7.1.2 packaging information ............................. 266 ranges of supply voltage and operating submit documentation feedback contents 5
revision history 2 device overview 2.1 device characteristics tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com note: page numbers for previous revisions may differ from page numbers in the current version. this data manual revision history highlights the technical changes made to the sprs343b device-specific data manual to make it an sprs343c revision. scope: applicable updates to the tms320dm643x dmp, specifically relating to the tms320dm6433 device, have been incorporated. added 660- and 700-mhz c64x+? device speeds. added designators for low-power (-l) devices. see additions/modifications/deletions section 1.1 added "5280, 5600 mips" to "high-performance digital signal processor (dm6437)" bullet section 1.2 in first paragraph, updated/changed the following: ? first sentence from "with performance up to 4800 million instructions per second (mips) at a clock rate of 600 mhz..." to "with performance up to 5600 million instructions per second (mips) with a clock rate of 700 mhz..." ? fifth sentence from "the dsp core can produce...for a total of 2400 million macs per second...or a total of 4800 mmacs." to "the dsp core can produce...for a total of 2800 million macs per second...or a total of 5600 mmacs." section 2.6 table 2-23 , multichannel audio serial port (mcasp0) terminal functions: updated/changed afsr0/dr0/gp[100] pin description from "... frame synchronization afsx0..." to "...frame synchronization afsr0..." updated/changed afsx0/dx1/gp[107] pin description from "...frame synchronization afsr0..." to "...frame synchronization afsx0..." table 2-20 , dac [part of vpbe] terminal functions: updated/changed v dda_1p1v description section 2.8 updated/changed figure 2-10 , device nomenclature, to reflect new device speeds and low-power designator (-l suffix). section 5 added footnote to section 5.1 , absolute maximum ratings over operating temperature range (unless otherwise noted) section 5 updated/changed i cdd and i ddd test conditions and footnote in section 5.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature (unless otherwise noted). section 6.7.1 table 6-15 , pllc1 clock frequency ranges: updated/changed pllout 1.2v-cv dd max value from "700 mhz" to "600 mhz" for -6/-5/-4/-l/-q6/-q5/-q4 devices. updated/changed sysclk1 1.05v-cv dd max value from "560 mhz" to "520 mhz" for -7 devices. section 5.2 deleted "future variants..." footnote from table section 6.7.1 updated/changed sentence from "ti requires emi filter manufacturer murata..." to "ti recommends emi filter manufacturer murata..." section 6.7.4 deleted "(-4, -4q, -4s, -5, -5q, -5s, -6)" from table 6-19 title, timing requirements for mxi/clkin. table 2-1 , provides an overview of the tms320dm6433 dsp. the tables show significant features of the dm6433 device, including the capacity of on-chip ram, the peripherals, the cpu frequency, and the package type with pin count. revision history 6 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-1. characteristics of the dm6433 processor hardware features dm6433 ddr2 memory controller (16-/32-bit bus width) [1.8 v i/o] asynchronous (8-bit bus width), asynchronous emif [emifa] ram, flash, (8-bit nor or 8-bit nand) edma3 1 (64 independent channels, 8 qdma channels) 2 64-bit general purpose timers (configurable as 2 64-bit or 4 32-bit) 1 64-bit watch dog uart 1 (with rts and cts flow control) peripherals i2c 1 (master/slave) not all peripherals pins mcbsp 1 are available at the same time (for more detail, see mcasp 1 (4 serailizers) the device configuration 10/100 ethernet mac (emac) with section). 1 management data input/output (mdio) vlynq 1 general-purpose input/output port (gpio) up to 111 pins pwm 3 outputs hpi (16-bit) 1 pci (32-bit), [33-mhz] 1 configurable video port 1 output (vpbe) size (bytes) 240kb ram, 64kb rom 32k-byte (32kb) l1 program (l1p) ram/cache (cache up to 32kb) on-chip memory organization 80kb l1 data (l1d) ram/cache (cache up to 32kb) 128kb unified mapped ram/cache (l2) 64kb boot rom revision id register (mm_revid.[15:0]) see the tms320dm6437/35/33/31 digital media megamodule rev id (address location: 0x0181 2000) processor (dmp) [silicon revisions 1.1 and 1.0] silicon errata (literature number sprz250 ). cpu id + cpu rev id control status register (csr.[31:16]) jtagid register see section 6.23.1 , jtag id (jtagid) register jtag bsdl_id (address location: 0x01c4 0028) description(s) 700 (-7) 660 (-q6) cpu frequency (1) (2) mhz 600 (-6/-l) 500 (-5/-q5) 400 (-4/-q4) 2.5 ns (-4/-q4) 2 ns (-5/-q5) cycle time (1) (2) ns 1.67 ns (-6/-l) 1.51 ns (-q6) 1.43 ns (-7) 1.2 v (-7/ -6/-5/ -4/-l/-q6/-q5/-q4) core (v) voltage 1.05 v (-7/-6/-5/-4/-l/-q5) i/o (v) 1.8 v, 3.3 v mxi/clkin frequency multiplier pll options x1 (bypass), x14 to x 30 (27 mhz reference) 16 x 16 mm, 0.8 mm pitch 361-pin bga (zwt) bga package(s) 23 x 23 mm, 1.0 mm pitch 376-pin bga (zdu) process technology m 0.09 m (1) performance numbers assume core voltage is set to 1.2v (2) applies to "tape and reel" part number counterparts as well. for more information, see section 2.8 , device and development-support tool nomenclature. submit documentation feedback device overview 7
2.2 cpu (dsp core) description tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-1. characteristics of the dm6433 processor (continued) hardware features dm6433 product preview (pp), advance information (ai), product status (3) pd or production data (pd) (3) production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. the c64x+ central processing unit (cpu) consists of eight functional units, two register files, and two data paths as shown in figure 2-1 . the two general-purpose register files (a and b) each contain 32 32-bit registers for a total of 64 registers. the general-purpose registers can be used for data or can be data address pointers. the data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 lsbs of data placed in an even register and the remaining 8 or 32 msbs in the next upper register (which is always an odd-numbered register). the eight functional units (.m1, .l1, .d1, .s1, .m2, .l2, .d2, and .s2) are each capable of executing one instruction every clock cycle. the .m functional units perform all multiply operations. the .s and .l units perform a general set of arithmetic, logical, and branch functions. the .d units primarily load data from memory to the register file and store results from the register file into memory. the c64x+ cpu extends the performance of the c64x core through enhancements and new features. each c64x+ .m unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). there is also support for galois field multiplication for 8-bit and 32-bit data. many communications algorithms such as ffts and modems require complex multiplication. the complex multiply (cmpy) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. there are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. the 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types. the .l or (arithmetic logic unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. there are also saturated forms of these instructions. the c64x+ core enhances the .s unit in several ways. in the c64x core, dual 16-bit min2 and max2 comparisons were only available on the .l units. on the c64x+ core they are also available on the .s unit which increases the performance of algorithms that do searching and sorting. finally, to increase data packing and unpacking throughput, the .s unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. unpack instructions prepare 8-bit data for parallel 16-bit operations. pack instructions return parallel results to output precision including saturation support. other new features include: sploop - a small instruction buffer in the cpu that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. the sploop buffer reduces the code size associated with software pipelining. furthermore, loops in the sploop buffer are fully interruptible. compact instructions - the native instruction size for the c6000 devices is 32 bits. many common instructions such as mpy, and, or, add, and sub can be expressed as 16 bits if the c64x+ compiler can restrict the code to use certain registers in the register file. this compression is performed by the code generation tools. instruction set enhancement - as noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit galois field multiplication. device overview 8 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 exceptions handling - intended to aid the programmer in isolating bugs. the c64x+ cpu is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). privilege - defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. local memory is divided into multiple pages, each with read, write, and execute permissions. time-stamp counter - primarily targeted for real-time operating system (rtos) robustness, a free-running time-stamp counter is implemented in the cpu which is not sensitive to system stalls. for more details on the c64x+ cpu and its enhancements over the c64x architecture, see the following documents: tms320c64x/c64x+ dsp cpu and instruction set reference guide (literature number spru732 ) tms320c64x+ dsp megamodule reference guide (literature number spru871 ) tms320c64x to tms320c64x+ cpu migration guide application report (literature number spraa84 ) tms320c64x+ dsp cache user's guide (literature number spru862 ) submit documentation feedback device overview 9
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 2-1. tms320c64x+? cpu (dsp core) data paths 10 device overview submit documentation feedback src2 src2 .d1 .m1 .s1 .l1 long src odd dst src2 src1 src1src1 src1 even dsteven dst odd dst dst1 dst src2src2 src2 long src da1 st1bld1b ld1a st1a data path a odd register file a (a1, a3, a5...a31) odd register file b (b1, b3, b5...b31) .d2 src1 dst src2 da2 ld2a ld2b src2 .m2 src1 dst1 .s2 src1 even dst long src odd dst st2a st2b long src .l2 even dst odd dst src1 data path b control register 32 msb 32 lsb dst2 (a) 32 msb 32 lsb 2x1x 32 lsb 32 msb 32 lsb 32 msb dst2 (b) (b) (a) 8 8 8 8 32 32 32 32 (c) (c) even register file a (a0, a2, a4...a30) even register file b (b0, b2, b4...b30) (d) (d) (d) (d) a. on .m unit, dst2 is 32 msb. b. on .m unit, dst1 is 32 lsb. c. on c64x cpu .m unit, src2 is 32 bits; on c64x+ cpu .m unit, src2 is 64 bits. d. on .l and .s units, odd dst connects to odd register files and even dst connects to even register files.
2.3 c64x+ cpu tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the c64x+ core uses a two-level cache-based architecture. the level 1 program memory/cache (l1p) consists of 32 kb memory space that can be configured as mapped memory or direct mapped cache. the level 1 data memory/cache (l1d) consists of 80 kb?48 kb of which is mapped memory and 32 kb of which can be configured as mapped memory or 2-way set associated cache. the level 2 memory/cache (l2) consists of a 128 kb memory space that is shared between program and data space. l2 memory can be configured as mapped memory, cache, or a combination of both. table 2-2 shows a memory map of the c64x+ cpu cache registers for the device. table 2-2. c64x+ cache registers hex address range register acronym description 0x0184 0000 l2cfg l2 cache configuration register 0x0184 0020 l1pcfg l1p size cache configuration register 0x0184 0024 l1pcc l1p freeze mode cache configuration register 0x0184 0040 l1dcfg l1d size cache configuration register 0x0184 0044 l1dcc l1d freeze mode cache configuration register 0x0184 0048 - 0x0184 0ffc - reserved 0x0184 1000 edmaweight l2 edma access control register 0x0184 1004 - 0x0184 1ffc - reserved 0x0184 2000 l2alloc0 l2 allocation register 0 0x0184 2004 l2alloc1 l2 allocation register 1 0x0184 2008 l2alloc2 l2 allocation register 2 0x0184 200c l2alloc3 l2 allocation register 3 0x0184 2010 - 0x0184 3fff - reserved 0x0184 4000 l2wbar l2 writeback base address register 0x0184 4004 l2wwc l2 writeback word count register 0x0184 4010 l2wibar l2 writeback invalidate base address register 0x0184 4014 l2wiwc l2 writeback invalidate word count register 0x0184 4018 l2ibar l2 invalidate base address register 0x0184 401c l2iwc l2 invalidate word count register 0x0184 4020 l1pibar l1p invalidate base address register 0x0184 4024 l1piwc l1p invalidate word count register 0x0184 4030 l1dwibar l1d writeback invalidate base address register 0x0184 4034 l1dwiwc l1d writeback invalidate word count register 0x0184 4038 - reserved 0x0184 4040 l1dwbar l1d block writeback 0x0184 4044 l1dwwc l1d block writeback 0x0184 4048 l1dibar l1d invalidate base address register 0x0184 404c l1diwc l1d invalidate word count register 0x0184 4050 - 0x0184 4fff - reserved 0x0184 5000 l2wb l2 writeback all register 0x0184 5004 l2wbinv l2 writeback invalidate all register 0x0184 5008 l2inv l2 global invalidate without writeback 0x0184 500c - 0x0184 5027 - reserved 0x0184 5028 l1pinv l1p global invalidate 0x0184 502c - 0x0184 5039 - reserved 0x0184 5040 l1dwb l1d global writeback 0x0184 5044 l1dwbinv l1d global writeback with invalidate 0x0184 5048 l1dinv l1d global invalidate without writeback submit documentation feedback device overview 11
2.4 memory map summary tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-2. c64x+ cache registers (continued) hex address range register acronym description 0x0184 8000 - 0x0184 80bc mar0 - mar47 reserved (corresponds to byte address 0x0000 0000 - 0x2fff ffff) memory attribute registers for pci data (corresponds to byte address 0x0184 80c0 - 0x0184 80fc mar48 - mar63 0x3000 0000 - 0x3fff ffff) 0x0184 8100 - 0x0184 8104 mar64 - mar65 reserved (corresponds to byte address 0x4000 0000 - 0x41ff ffff) memory attribute registers for emifa 0x0184 8108 - 0x0184 8124 mar66 - mar73 (corresponds to byte address 0x4200 0000 - 0x49ff ffff) 0x0184 8128 - 0x0184 812c mar74 - mar75 reserved (corresponds to byte address 0x4a00 0000 - 0x4bff ffff) memory attribute registers for vlynq (corresponds to byte address 0x0184 8130 - 0x0184 813c mar76 - mar79 0x4c00 0000 - 0x4fff ffff) 0x0184 8140- 0x0184 81fc mar80 - mar127 reserved (corresponds to byte address 0x5000 0000 - 0x7fff ffff) memory attribute registers for ddr2 0x0184 8200 - 0x0184 823c mar128 - mar143 (corresponds to byte address 0x8000 0000 - 0x8fff ffff) 0x0184 8240 - 0x0184 83fc mar144 - mar255 reserved (corresponds to byte address 0x9000 0000 - 0xffff ffff) table 2-3 shows the memory map address ranges of the device. table 2-4 depicts the expanded map of the configuration space (0x0180 0000 through 0x0fff ffff). the device has multiple on-chip memories associated with its two processors and various subsystems. to help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. 12 device overview submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-3. memory map summary start end size c64x+ edma peripheral vpss pci address address (bytes) memory map memory map memory map memory map 0x0000 0000 0x000f ffff 1m reserved 0x0010 0000 0x0010 ffff 64k boot rom 0x0011 0000 0x007f ffff 7m-64k reserved 0x0080 0000 0x0081 ffff 128k l2 ram/cache (1) 0x0082 0000 0x00e0 7fff 6048k reserved 0x00e0 8000 0x00e0 ffff 32k l1p ram/cache (1) reserved reserved 0x00e1 0000 0x00f0 3fff 976k reserved 0x00f0 4000 0x00f0 ffff 48k l1d ram 0x00f1 0000 0x00f1 7fff 32k l1d ram/cache (1) 0x00f1 8000 0x017f ffff 9120k reserved 0x0180 0000 0x01bf ffff 4m cfg space 0x01c0 0000 0x01ff ffff 4m cfg bus peripherals cfg bus peripherals cfg bus peripherals 0x0200 0000 0x100f ffff 225m reserved 0x1010 0000 0x1010 ffff 64k boot rom reserved reserved 0x1011 0000 0x107f ffff 7m-48k reserved 0x1080 0000 0x1081 ffff 128k l2 ram/cache (1) l2 ram/cache (1) l2 ram/cache (1) 0x1082 0000 0x10e0 7fff 6048k reserved reserved reserved 0x10e0 8000 0x10e0 ffff 32k l1p ram/cache (1) l1p ram/cache (1) l1p ram/cache (1) 0x10e1 0000 0x10f0 3fff 976k reserved reserved reserved reserved 0x10f0 4000 0x10f0 ffff 48k l1d ram l1d ram l1d ram 0x10f1 0000 0x10f1 7fff 32k l1d ram/cache (1) l1d ram/cache (1) l1d ram/cache (1) 0x10f1 8000 0x10ff ffff 1m-96k reserved reserved reserved 0x1100 0000 0x1fff ffff 240m reserved reserved reserved 0x2000 0000 0x2000 7fff 32k ddr2 control regs ddr2 control regs ddr2 control regs 0x2000 8000 0x2fff ffff 256m-32k reserved reserved reserved 0x3000 0000 0x3fff ffff 256m pci data pci data 0x4000 0000 0x41ff ffff 32m reserved reserved 0x4200 0000 0x42ff ffff 16m emifa data ( cs2) (2) emifa data ( cs2) (2) 0x4300 0000 0x43ff ffff 16m reserved reserved 0x4400 0000 0x44ff ffff 16m emifa data ( cs3) (2) emifa data ( cs3) (2) 0x4500 0000 0x45ff ffff 16m reserved reserved 0x4600 0000 0x46ff ffff 16m emifa data ( cs4) (2) emifa data ( cs4) (2) 0x4700 0000 0x47ff ffff 16m reserved reserved 0x4800 0000 0x48ff ffff 16m emifa data ( cs5) (2) emifa data ( cs5) (2) 0x4900 0000 0x49ff ffff 16m reserved reserved 0x4a00 0000 0x4bff ffff 32m reserved reserved 0x4c00 0000 0x4fff ffff 64m vlynq (remote data) vlynq (remote data) 0x5000 0000 0x7fff ffff 768m reserved reserved 0x8000 0000 0x8fff ffff 256m ddr2 memory controller ddr2 memory controller ddr2 memory controller ddr2 memory controller 0x9000 0000 0xffff ffff 1792m reserved reserved reserved reserved (1) for all bootmodes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram (l2cfg.l2mode = 0h, l1pcfg.l1pmode = 0h, and l1dcfg.l1dmode = 0h). if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). for the emifa rom direct boot (bootmode[3:0] = 0100, fastboot = 0), the bootloader is not executed?that is, l2 ram/cache defaults to all ram (l2cfg.l2mode = 0h); l1p ram/cache defaults to all cache (l1pcfg.l1pmode = 7h); and l1d ram/cache defaults to all cache (l1dcfg.l1dmode = 7h). (2) the emifa cs0 and cs1 are not functionally supported on the dm6433 device, and therefore, are not pinned out. submit documentation feedback device overview 13
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-4. configuration memory map summary start end size c64x+ address address (bytes) 0x0180 0000 0x0180 ffff 64k c64x+ interrupt controller 0x0181 0000 0x0181 0fff 4k c64x+ powerdown controller 0x0181 1000 0x0181 1fff 4k c64x+ security id 0x0181 2000 0x0181 2fff 4k c64x+ revision id 0x0182 0000 0x0182 ffff 64k c64x+ emc 0x0183 0000 0x0183 ffff 64k reserved 0x0184 0000 0x0184 ffff 64k c64x+ memory system 0x0185 0000 0x0187 ffff 192k reserved 0x0188 0000 0x01bb ffff 3328k reserved 0x01bc 0000 0x01bc 00ff 256 reserved 0x01bc 0100 0x01bc 01ff 256 pin manager and trace 0x01bc 0400 0x01bf ffff 255k reserved 0x01c0 0000 0x01c0 ffff 64k edma cc 0x01c1 0000 0x01c1 03ff 1k edma tc0 0x01c1 0400 0x01c1 07ff 1k edma tc1 0x01c1 0800 0x01c1 0bff 1k edma tc2 0x01c1 0c00 0x01c1 9fff 5k reserved 0x01c1 a000 0x01c1 a7ff 2k pci control registers (1) 0x01c1 a800 0x01c1 ffff 22k reserved 0x01c2 0000 0x01c2 03ff 1k uart0 0x01c2 0400 0x01c2 07ff 1k reserved 0x01c2 0800 0x01c2 0fff 2k reserved 0x01c2 1000 0x01c2 13ff 1k i2c 0x01c2 1400 0x01c2 17ff 1k timer0 0x01c2 1800 0x01c2 1bff 1k timer1 0x01c2 1c00 0x01c2 1fff 1k timer2 (watchdog) 0x01c2 2000 0x01c2 23ff 1k pwm0 0x01c2 2400 0x01c2 27ff 1k pwm1 0x01c2 2800 0x01c2 2bff 1k pwm2 0x01c2 2c00 0x01c3 ffff 117k reserved 0x01c4 0000 0x01c4 07ff 2k system module 0x01c4 0800 0x01c4 0bff 1k pll controller 1 0x01c4 0c00 0x01c4 0fff 1k pll controller 2 0x01c4 1000 0x01c4 1fff 4k power and sleep controller 0x01c4 2000 0x01c6 6fff 148k reserved 0x01c6 7000 0x01c6 77ff 2k gpio 0x01c6 7800 0x01c6 7fff 2k hpi 0x01c6 8000 0x01c6 ffff 32k reserved 0x01c7 0000 0x01c7 3fff 16k vpss registers 0x01c7 4000 0x01c7 ffff 48k reserved 0x01c8 0000 0x01c8 0fff 4k emac control registers 0x01c8 1000 0x01c8 1fff 4k emac control module registers 0x01c8 2000 0x01c8 3fff 8k emac control module ram 0x01c8 4000 0x01c8 47ff 2k mdio control registers 0x01c8 4800 0x01cf ffff 494k reserved (1) access to certain pci registers when there is no active pci clock may hang the device. for more information, see the tms320dm643x peripheral component interconnect (pci) reference guide (literature number spru985). device overview 14 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-4. configuration memory map summary (continued) start end size c64x+ address address (bytes) 0x01d0 0000 0x01d0 07ff 2k mcbsp0 0x01d0 0800 0x01d0 0fff 2k reserved 0x01d0 1000 0x01d0 13ff 1k mcasp0 control 0x01d0 1400 0x01d0 17ff 1k mcasp0 data 0x01d0 1800 0x01df ffff 1018k reserved 0x01e0 0000 0x01e0 0fff 4k emifa control 0x01e0 1000 0x01e0 1fff 4k vlynq control registers 0x01e0 2000 0x0fff ffff 226m-8k reserved submit documentation feedback device overview 15
2.5 pin assignments 2.5.1 pin map (bottom view) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. for more information on pin muxing, see tbd, multiplexed pin configurations of this document. figure 2-2 through figure 2-5 show the bottom view of the zwt package pin assignments in four quadrants (a, b, c, and d). figure 2-6 through figure 2-9 show the bottom view of the zdu package pin assignments in four quadrants (a, b, c, and d). figure 2-2. zwt pin map [quadrant a] device overview 16 submit documentation feedback w v u t r p nm l k 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 ddr_d[3] v ss tout1l/ gp[55] v ss ucts0/ gp[87] utxd0/ gp[86] urxd0/ gp[85] scl sda tck resetout emu1 por dv dd33 tdo emu0 trst dv ddr2 tms ddr_d[1] ddr_dqm[0] ddr_d[2] pcien tdi reset rsv3 tinp1l/ gp[56] rsv2 cv dd v ss v ss v ss cv dd dv ddr2 ddr_a[11] ddr_a[12] ddr_clk ddr_clk ddr_d[14] v ss dv dd33 v ss ddr_d[5] ddr_d[6] ddr_d[9] v ss v ss dv ddr2 ddr_ba[2] v ss ddr_d[11] ddr_d[15] ddr_cke cv dd v ss cv dd cv dd v ss ddr_dqm[1] ddr_cas ddr_we ddr_zn v ss v ss ddr_dqs[1] ddr_ras ddr_a[10] cv dd cv dd dv ddr2 ddr_d[4] ddr_d[8] ddr_d[13] ddr_ba[1] ddr_d[12] dv ddr2 tinp0l/ gp[98] v ss v ss v ss dv ddr2 clkout0/ pwm2/ gp[84] dv dd33 v ss dv dd33 dv ddr2 dv ddr2 v ss dv ddr2 ddr_cs cv dd ddr_dqs[0] ddr_d[10] ddr_ba[0] ddr_d[0] urts0/ pwm0/ gp[88] ddr_d[7] w v u t r p nm l k v ss v ss ddr_a[8] ddr_a[8]
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 2-3. zwt pin map [quadrant b] submit documentation feedback device overview 17 w v u t r p nm l k 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 v ssa_1p1v cv dd v ss v ss cv dd v ss cv dd v ss v ss v ss dv ddr2 v ss rsv5 dv ddr2 ddr_zp ddr_vssdll ddr_vdddll dv ddr2 cv dd dv ddr2 v ss v ss v ss v ss v ss dac_iout_c dac_vref dac_iout_b dv ddr2 dv ddr2 ddr_d[27] ddr_d[21] ddr_d[18] dac_iout_a rsv4 dv ddr2 v ss dv ddr2 ddr_dqs[2] ddr_d[28] mxv dd ddr_d[17] ddr_d[22] ddr_d[24] v ss v ss v dda_1p8v dac_iout_d v ss dac_rbias ddr_vref ddr_dqm[3] ddr_d[23] ddr_d[31] dv dd33 mxi/ clkin ddr_d[20] ddr_dqs[3] ddr_d[30] v ss v ss ddr_d[19] ddr_d[29] ddr_d[16] v ss cv dd dv dd33 v ss pll pwr18 v ss v ss dv dd33 v dda_1p1v v ss v ssa_1p8v v ss ddr_d[26] mxv ss ddr_dqm[2] ddr_d[25] cv dd w v u t r p nm l k ddr_a[0]ddr_a[1] ddr_a[2] ddr_a[5]ddr_a[3] ddr_a[4] ddr_a[6]ddr_a[9] ddr_a[7]
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 2-4. zwt pin map [quadrant c] 18 device overview submit documentation feedback h g f e dc b a 19 18 17 16 15 14 13 12 11 19 18 17 16 15 14 13 12 11 cv dd em_wait/ (rdy/bsy ) gp[53] gp[43] em_a[15]/ ad29/ em_d[2]/ gp[49] em_a[16]/ pgnt / em_d[3]/ gp[48] em_a[20]/ pinta / em_d[7]/ gp[44] em_a[21]/ gp[34] em_a[18]/ prst / em_d[5]/ gp[46] em_r/w / gp[35] ad30 ad28 dv dd33 dv dd33 v ss v ss v ss dv dd33 v ss gp[41] gp[39] gp[42] gp[54] lcd_oe/em_cs3 / gp[13] g0/ em_cs2 / gp[12] yout0/ gp[22]/ (bootmode0) cout1/ em_d[1]/ gp[15] vclk/ gp[31] cout4/ em_d[4]/ gp[18] vsync/ em_cs4 / gp[32] gp[37] cout6/ em_d[6]/ gp[20] v ss gp[40] v ss dv dd33 dv dd33 b0/ lcd_field/ em_a[3]/ gp[11] g1/ em_a[1]/ (ale)/gp[9]/ (aeaw1/ pllms1) cout5/ em_d[5]/ gp[19] cout2/ em_d[2]/ gp[16] b2/ em_ba[1]/ gp[5]/ (aem0) cout0/ em_d[0]/ gp[14] yout2/ gp[24]/ (bootmode2) yout3/ gp[25]/ (bootmode3) yout4/ gp[26]/ (fastboot) vpbeclk/ gp[30] r0/ em_a[4]/ gp[10]/ (aeaw2/ pllms2) v ss yout7/ gp[29] yout6/ gp[28] v ss r1/ em_a[0]/ gp[7]/ (aem2) v ss em_a[17]/ ad31/ em_d[4]/ gp[47] gp[52] r2/ em_ba[0]/ gp[6]/ (aem1) b1/ em_a[2]/ (cle)/gp[8]/ (aeaw0/ pllms0) cout7/ em_d[7]/ gp[21] gp[38] gp[36] em_oe em_we cout3/ em_d[3]/ gp[17] yout1/ gp[23]/ (bootmode1) v ss dv dd33 cv dd v ss yout5/ gp[27]/ (lendian) em_a[19]/ preq / em_d[6]/ gp[45] h g f e dc b a j v ss cv dd v ss v ss dv dd33 mxo v ss dv dd33 v ss j hsync/ em_cs5 / gp[33]
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 2-5. zwt pin map [quadrant d] submit documentation feedback device overview 19 j hg fe dc ba 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 axr0[0]/ gp[105] dv dd33 hd15/ mtxclk/ ad12/ gp[73] dv dd33 v ss hr/w / mrxclk/ ad8/ gp[77] hds1 / mrxd1/ ad7/ gp[79] hint / mrxd3/ ad6/ gp[82] hds2 / mrxd0/ ad9/ gp[78] has / mdio/ ad3/ gp[83] hcntl1/ mtxen/ ad11/ gp[75] hrdy / mrxd2/ pcbe0 / gp[80] hd14/ mtxd0/ ad15/ gp[72] ad0/ gp[0] ad2/ gp[2] ad1/ gp[1] amutein0/ gp[109] v ss gp[4]/ pwm1 afsx0/ gp[107] axr0[3]/ fsr0/ gp[102] aclkr0/ clkx0/ gp[99] amute0/ gp[110] ad4/ gp[3] hhwil/ mrxdv/ ad13/ gp[74] hd10/ mcrs/ pserr / gp[68] hd13/ mtxd1/ ad14/ gp[71] hd8/ vlynq_txd3/ pperr / gp[66] em_a[7]/ ad22/ gp[94] em_a[11]/ ad24/ gp[90] em_a[9]/ pidsel/ gp[92] em_a[12]/ pcbe3 / gp[89] v ss ad26 hd7/ vlynq_txd2/ pdevsel / gp[65] dv dd33 axr0[2]/ fsx0/ gp[103] axr0[1]/ dx0/ gp[104] hd12/ mtxd2/ ppar/ gp[70] dv dd33 v ss cv dd em_a[8]/ ad21/ gp[93] v ss v ss cv dd cv dd vlynq_ clock/ pciclk/ gp[57] dv dd33 em_a[6]/ ad20/ gp[95] hd4/ vlynq_rxd3/ pframe / gp[62] hd1/ vlynq_rxd0/ ad16/ gp[59] dv dd33 v ss dv dd33 dv dd33 hd2/ vlynq_rxd1/ ad17/ gp[60] em_a[14]/ ad27/ em_d[1]/ gp[50] v ss cv dd v ss em_a[5]/ ad19/ gp[96] em_a[13]/ ad25/ em_d[0]/ gp[51] dv dd33 ahclkr0/ clkr0/ gp[101] clks0/ tout0l/ gp[97] dv dd33 v ss v ss dv dd33 hd5/ vlynq_txd0/ pirdy / gp[63] hd0/ vlynq_ scrun/ ad18/ gp[58] hd3/ vlynq_rxd2/ pcbe2 / gp[61] v ss hcs / mdclk/ ad5/ gp[81] hd11/ mtxd3/ pcbe1 / gp[69] hd9/ mcol/ pstop / gp[67] hd6/ vlynq_txd1/ ptrdy / gp[64] rsv1 v ss aclkx0/ gp[106] v ss v ss afsr0/ dr0/ gp[100] dv dd33 v ss ahclkx0/ gp[108] hcntl0/ mrxer/ ad10/ gp[76] j h g f e dc ba dv dd33 em_a[10]/ ad23/ gp[91]
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 2-6. zdu pin map [quadrant a] 20 device overview submit documentation feedback m n p r t u v 11 10 9 4 3 11 10 9 8 7 6 5 4 3 m n v w w y y 2 1 2 1 aa aa ab ab m n p r t u p 11 5 10 9 8 7 6 clkout0/ pwm2/ gp[84] reset resetout por tms tdo tdi tck trst emu1 emu0 pcien dv dd33 dv dd33 dv dd33 dv dd33 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 urts0/ pwm0/ gp[88] tinp1l/ gp[56] tout1l/ gp[55] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss cv dd v ss v ss v ss v ss v ss rsv3 ucts0/ gp[87] utxd0/ gp[86] urxd0/ gp[85] sda scl ddr_d[0] ddr_d[1] ddr_d[2] ddr_d[3] ddr_d[4] ddr_d[5] ddr_d[6] ddr_d[7] ddr_d[8] ddr_d[9] ddr_d[10] ddr_d[11] ddr_d[12] ddr_d[13]ddr_d[14] ddr_d[15] ddr_a[11] ddr_a[10] ddr_a[12] ddr_bs[2] ddr_bs[1]ddr_bs[0] ddr_dqs[1] ddr_dqs[0] ddr_cas ddr_ras ddr_dqm[0] ddr_dqm[1] ddr_cs ddr_we ddr_cke ddr_clk0 ddr_clk0 cv dd cv dd v ss cv dd v ss v ss cv dd
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 2-7. zdu pin map [quadrant b] submit documentation feedback device overview 21 m n p r t u v 12 13 14 19 20 12 13 14 15 16 17 18 19 20 m n v w w y y 21 22 21 22 aa aa ab ab m n p r t u p 12 18 13 14 15 16 17 mxi/ clkin mxo mxv ss pll pwr18 dac_vref dac_iout_a dac_iout_b dac_iout_c dac_iout_d v dda_1p8v v ssa_1p8v v dda_1p1v v ssa_1p1v dac_rbias dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 mxv dd dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 dv ddr2 cv dd cv dd cv dd cv dd v ss v ss v ss ddr_d[24] ddr_d[20] ddr_dqm[2] ddr_a[5] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss rsv4 v ss v ss v ss v ss rsv5 ddr_zp ddr_zn ddr_vdddll ddr_vssdll ddr_vref ddr_d[16]ddr_d[17] ddr_d[18] ddr_d[19] ddr_d[21] ddr_d[22] ddr_d[23] ddr_d[25] ddr_d[26] ddr_d[27] ddr_d[28] ddr_d[29] ddr_d[30] ddr_d[31] ddr_a[0] ddr_a[1] ddr_a[2] ddr_a[3] ddr_a[4]ddr_a[6] ddr_a[7] ddr_a[8] ddr_a[9] ddr_dqs[3] ddr_dqs[2] ddr_dqm[3] v ss
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 2-8. zdu pin map [quadrant c] 22 device overview submit documentation feedback l k j h g fe 12 13 14 19 20 12 13 14 15 16 17 18 19 20 l k e d v ss r2/ em_ba[0]/ gp[6]/ (aem1) dv dd33 dv dd33 ad30 ad28 em_oe v ss ad26 d c em_r/w / gp[35] b2/ em_ba[1]/ gp[5[/ (aem0) em_a[21]/ gp[34] em_a[19]/ preq / em_d[6]/ gp[45] em_a[15]/ ad29/ em_d[2]/ gp[49] em_we em_a[20]/ pinta / em_d[7]/ gp[44] em_a[11]/ ad24/ gp[90] c 21 22 21 22 cout2/ em_d[2]/ gp[16] cout5/ em_d[5]/ gp[19] cout6/ em_d[6]/ gp[20] cout4/ em_d[4]/ gp[18] vsync/ em_cs4 / gp[32] hsync/ em_cs5 / gp[33] yout7/ gp[29] dv dd33 cout0/ em_d[0]/ gp[14] vclk/ gp[31] vpbeclk/ gp[30] v ss lcd_oe/ em_cs3 / gp[13] b0/ lcd_field/ em_a[3]/ gp[11] g0/ em_cs2 / gp[12] b gp[38] gp[40]gp[37] em_a[17]/ ad31/ em_d[4]/ gp[47] em_a[16]/ pgnt / em_d[3]/ gp[48] gp[36] gp[42] em_a[12]/ pcbe3 / gp[89] b a gp[43] gp[54] gp[39] em_a[18]/ prst / em_d[5]/ gp[46] em_a[14]/ ad27/ em_d[1]/ gp[50] gp[52] gp[53] em_a[13]/ ad25/ em_d[0]/ gp[51] a v ss v ss dv dd33 13 14 15 16 17 lk j hg f j 12 18 yout5/ gp[27]/ (lendian) yout3/ gp[25]/ (bootmode3) yout2/ gp[24]/ (bootmode2) yout1/ gp[23]/ (bootmode1) yout6/ gp[28] yout4/ gp[26]/ (fastboot) r0/ em_a[4]/ gp[10]/ (aeaw2/ pllms2) g1/ em_a[1]/ (ale)/gp[9]/ (aeaw1/ pllms1) b1/ em_a[2]/ (cle)/gp[8]/ (aeaw0/ pllms0) r1/ em_a[0]/ gp[7]/ (aem2) em_wait/ (rdy/bsy ) yout0/ gp[22]/ (bootmode0) dv dd33 dv dd33 dv dd33 v ss v ss v ss v ss dv dd33 v ss v ss dv dd33 dv dd33 v ss dv dd33 dv dd33 dv dd33 cv dd cv dd cv dd v ss cv dd cv dd v ss v ss v ss v ss v ss cout7/ em_d[7]/ gp[21] cout3/ em_d[3]/ gp[17] cout1/ em_d[1]/ gp[15] gp[41]
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 2-9. zdu pin map [quadrant d] submit documentation feedback device overview 23 l k j hg f e 11 10 9 4 3 11 10 9 8 7 6 5 4 3 l k e d dv dd33 hhwil/ mrxdv/ ad13/ gp[74] v ss dv dd33 rsv1 dv dd33 v ss d c hd9/ mcol/ pstop / gp[67] hrdy / mrxd2/ pcbe0 / gp[80] hd12/ mtxd2/ ppar/ gp[70] hd6/ vlynq_txd1/ ptrdy / gp[64] hd1/ vlynq_rxd0 / ad16/ gp[59] em_a[7]/ ad22/ gp[94] hcntl1/ mtxen/ ad11/ gp[75] hd4/ vlynq_rxd3/ pframe / gp[62] em_a[9]/ pidsel/ gp[92] c 2 1 2 1 ad0/ gp[0] ad2/ gp[2] ad4/ gp[3] afsx0/ gp[107] ahclkx0/ gp[108] axr0[0]/ gp[105] aclkr0/ clkx0/ gp[99] axr0[2]/ fsx0/ gp[103] axr0[1]/ dx0/ gp[104] tinp0l/ gp[98] ad1/ gp[1] aclkx0/ gp[106] ahclkr0/ clkr0/ gp[101] dv dd33 has / mdio/ ad3/ gp[83] hint / mrxd3/ ad6/ gp[82] hcs / mdclk/ ad5/ gp[81] hds2 / mrxd0/ ad9/ gp[78] b hd10/ mcrs/ pserr / gp[68] hds1 / mrxd1/ ad7/ gp[79] hd14/ mtxd0/ ad15/ gp[72] hd7/ vlynq_txd2/ pdevsel / gp[65] hd0/ vlynq_ scrun/ ad18/ gp[58] em_a[6]/ ad20/ gp[95] hd13/ mtxd1/ ad14/ gp[71] hd3/ vlynq_rxd2/ pcbe2 / gp[61] em_a[10]/ ad23/ gp[91] b a hd8/ vlynq_txd3/ pperr / gp[66] hr/w / mrxclk/ ad8/ gp[77] hd11/ mtxd3/ pcbe1 / gp[69] hd5/ vlynq_txd0/ pi rdy / gp[63] hd2/ vlynq_rxd1/ ad17/ gp[60] em_a[5]/ ad19/ gp[96] hd15/ mtxclk/ ad12/ gp[73] vlynq_ clock/ pciclk/ gp[57] em_a[8]/ ad21/ gp[93] a dv dd33 hcntl0/ mrxer/ ad10/ gp[76] v ss dv dd33 11 10 9 8 7 6 l k jh g f j 5 dv dd33 dv dd33 dv dd33 dv dd33 v ss dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 dv dd33 gp[4]/ pwm1 clks0/ tout0l/ gp[97] v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss rsv2 amute0/ gp[110] amutein0/ gp[109] afsr0/ dr0/ gp[100] axr0[3]/ fsr0/ gp[102] cv dd cv dd cv dd cv dd
2.6 terminal functions tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the terminal functions tables (table 2-5 through table 2-31 ) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. for more detailed information on device configuration, peripheral selection, multiplexed/shared pin, and debugging considerations, see the device configurations section of this data manual. all device boot and configuration pins (except pcien) are multiplexed configuration pins? meaning they are multiplexed with functional pins. these pins function as device boot and configuration pins only during device reset. the input states of these pins are sampled and latched into the bootcfg register when device reset is deasserted (see note below). after device reset is deasserted, the values on these multiplexed pins no longer have to hold the configuration. the pcien pin is a standalone configuration pin. its value is latched into the bootcfg register when device reset is deasserted (see note below). unlike the multiplexed device boot and configuration pins, the value on the pcien pin even after device reset is deasserted must hold the configuration. for proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. section 3.9.1 , pullup/pulldown resistors discusses situations where external pullup/pulldown resistors are required. note: internal to the chip, the two device reset pins reset and por are logically and?d together for the purpose of latching device boot and configuration pins. the values on all device boot and configuration pins are latched into the bootcfg register when the logical and of reset and por transitions from low-to-high. table 2-5. boot terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. boot yout3/gp[25]/ (bootmode3) g16 h21 bootmode configuration bits. these bootmode functions along with yout2/gp[24]/ the fastboot function determine what device bootmode (bootmode2) g15 l20 ipd configuration is selected. i/o/z dv dd33 the dm6433 device supports several types of bootmodes along with yout1/gp[23]/ f15 k20 a fastboot option; for more details on the types/options, see (bootmode1) f18 j20 section 3.4.1 , boot modes. yout0/gp[22]/ (bootmode0) fast boot yout4/gp26]/ ipd g17 k19 i/o/z 0 = not fast boot (fastboot) dv dd33 1 = fast boot r0/em_a[4]/ emifa address bus width (aeaw) and fast boot pll multiplier ipd gp[10]/(aeaw2/pll a17 b21 i/o/z select (pllms). dv dd33 ms2) these configuration pins serve two purposes which are based on aem[2:0] settings. g1/em_a[1]/(ale)/ ipd for aem[2:0] = 001 [8-bit emifa (async) pinout mode 1], the gp[9]/ a16 b20 i/o/z dv dd33 aeaw/pllms pins serve as the aeaw function to select emifa (aeaw1/pllms1) address bus width. for all other aem modes, the aeaw/pllms pins select the pll b1/em_a[2]/(cle)/g ipd multiplier for fast boot. p[8]/ b16 a20 i/o/z dv dd33 for more details, see section 3.5.1.2 , emifa address width select (aeaw0/pllms0) (aeaw) and fast boot pll multipler select (pllms). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup.for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 24 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-5. boot terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. r1/em_a[0]/ ipd selects emifa pinout mode b17 c21 i/o/z gp[7]/(aem2) dv dd33 the dm6433 supports the following emifa pinout modes: r2/em_ba[0]/ ipd c17 e20 i/o/z aem[2:0] = 000, no emifa gp[6]/(aem1) dv dd33 aem[2:0] = 001, 8-bit emifa (async) pinout mode 1 aem[2:0] = 011, 8-bit emifa (async) pinout mode 3 aem[2:0] = 100, 8-bit emifa (nand) pinout mode 4 b2/em_ba[1]/ ipd aem[2:0] = 101, 8-bit emifa (nand) pinout mode 5 c16 c20 i/o/z gp[5]/(aem0) dv dd33 this signal doesn't actually affect the emifa module. it only affects how the emifa is pinned out. for proper dm6433 device operation, if this pin is both routed and 3-stated (not driven) during device reset, it must be pulled down via yout6/ ipd h16 j21 i/o/z an external resistor. for more detailed information on gp[28] dv dd33 pullup/pulldown resistors, see section 3.9.1 , pullup/pulldown resistors. pci enable ipd pcien t3 w3 i 0 = pci pin function is disabled [default] dv dd33 1 = pci pin function is enabled for proper dm6433 device operation, if this pin is both routed and ipu 3-stated (not driven) during device reset, it must be pulled up via an yout5/gp[27] h17 l19 i/o/z dv dd33 external resistor. for more detailed information on pullup/pulldown resistors, see section 3.9.1 , pullup/pulldown resistors. submit documentation feedback device overview 25
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-6. oscillator/pll terminal functions signal type (1) other (2) description zwt zdu name no. no. oscillator, pll crystal input mxi for mx oscillator (system oscillator, typically 27 mhz). mxi/ k19 n22 i mxv dd if the internal oscillator is bypassed, this is the external oscillator clock clkin input. (3) mxo j19 m22 o mxv dd crystal output for mx oscillator 1.8 v power supply for mx oscillator. on the board, this pin can be mxv dd l18 n21 s (4) connected to the same 1.8 v power supply as dv ddr2 . mxv ss k18 m21 gnd (4) ground for mx oscillator pll pwr18 l16 n20 s (4) 1.8 v power supply for plls (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal (3) for more information on external board connections, see section 6.6 , external clock input from mxi/clkin pin. (4) for more information, see the recommended operating conditions table table 2-7. clock generator terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. clock generator this pin is multiplexed between the system clock generator (pll1), pwm2, and gpio. clkout0/ ipd m1 r1 i/o/z for the system clock generator (pll1), it is clock output clkout0. this is pwm2/gp[84] dv dd33 configurable for 27 mhz or other 27 mhz-divided-down (/1 to /32) clock outputs. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 26 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-8. reset and jtag terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. reset ipu reset m4 r3 i device reset dv dd33 ? reset output status pin. the resetout pin indicates when the resetout n3 t3 o/z dv dd33 device is in reset. ipu por n4 r2 i power-on reset. dv dd33 jtag ipu jtag test-port mode select input. tms r3 v3 i dv dd33 for proper device operation, do not oppose the ipu on this pin. ? tdo p3 u2 o/z jtag test-port data output dv dd33 ipu tdi p4 u3 i jtag test-port data input dv dd33 ipu tck n1 u1 i jtag test-port clock input dv dd33 jtag test-port reset. for ieee 1149.1 jtag compatibility, see ipd trst r2 v2 i the ieee 1149.1 jtag compatibility statement portion of this data dv dd33 sheet ipu emu1 n2 t2 i/o/z emulation pin 1 dv dd33 ipu emu0 p2 t1 i/o/z emulation pin 0 dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 27
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-9. emifa terminal functions (boot configuration) signal type (1) other (2) (3) description zwt zdu name no. no. emifa: boot configuration r0/em_a[4]/ these pins are multiplexed between the vpbe (venc), emifa, and ipd gp[10]/ a17 b21 i/o/z gpio. when reset or por is asserted, these pins function as dv dd33 (aeaw2/pllms2) emifa configuration pins. at reset if aem[2:0] = 001 (emifa in 8-bit async mode), then the input states of aeaw[2:0] are sampled to set g1/em_a[1]/ ipd the emifa address bus width. on dm6433, aeaw[2:0] must be set (ale)/gp[9]/ a16 b20 i/o/z dv dd33 to 100b if aem[2:0] = 001b. after reset, these pins function as vpbe (aeaw1/pllms1) (venc), emifa, or gpio pin functions based on pin mux selection. b1/em_a[2]/ for more details on the aeaw/pllms functions, see section 3.5.1.2 , (cle)/gp[8]/ b16 a20 i/o/z dv dd33 emifa address bus width (aeaw) and fast boot pll multiplier (aeaw0/pllms0) select (pllms). b2/em_ba[1]/ ipd these pins are multiplexed between the vpbe (venc), emifa, and c16 c20 i/o/z gp[5]/(aem0) dv dd33 gpio. when reset or por is asserted, these pins function as emifa configuration pins. at reset, the input states of aem[2:0] are r2/em_ba[0]/ ipd c17 e20 i/o/z sampled to set the emifa pinout mode. gp[6]/(aem1) dv dd33 for more details, see section 3.5.1 , configurations at reset. after reset, these pins function as vpbe (venc), emifa, or gpio pin r1/ em_a[0]/ ipd functions based on pin mux selection. b17 c21 i/o/z gp[7]/(aem2) dv dd33 for more details on the aem functions, see section 3.5.1.1 , emifa pinout mode (aem[2:0]). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 28 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit async/nor (emifa pinout mode 1, aem[2:0] = 001) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., pcien, aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with asynchronous memories (i.e., nor flash). g0/ em_cs2/ ipd this is the chip select for the default boot and rom boot modes. c19 c22 i/o/z gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with asynchronous memories (i.e., nor flash). lcd_oe/ em_cs3/ ipd c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, it is chip select 4 output em_cs4 for use with asynchronous memories (i.e., nor flash). vsync/ em_cs4/ ipd e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, it is chip select 5 output em_cs5 for use with asynchronous memories (i.e., nor flash). hsync/ em_cs5/ ipd f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa and gpio. em_r/ w/ ipd d13 c17 i/o/z gp[35] dv dd33 for emifa, it is read/write output em_r/ w. em_wait/ ipu for emifa (async/nor), this pin is wait state extension input e15 d20 i/o/z (rdy/ bsy) dv dd33 em_wait. ipu em_oe d15 d19 i/o/z for emifa, it is output enable output em_oe. dv dd33 ipu em_we e14 c19 i/o/z for emifa, it is write enable output em_we. dv dd33 this pin is multiplexed between vpbe (venc), emifa, and gpio. r2/em_ba[0]/ ipd for emifa, this is the bank address 0 output (em_ba[0]). when c17 e20 i/o/z gp[6]/(aem1) dv dd33 connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. this pin is multiplexed between vpbe (venc), emifa, and gpio. b2/em_ba[1]/ ipd for emifa, this is the bank address 1 output em_ba[1]. when c16 c20 i/o/z gp[5]/(aem0) dv dd33 connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 29
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between emifa and gpio. ipd em_a[21]/gp[34] d12 c16 i/o/z dv dd33 for emifa, it is address bit 21 output em_a[21]. this pin is multiplexed between emifa, pci, and gpio. em_a[20]/ pinta/ ipd c12 c15 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 20 output em_d[7]/gp[44] dv dd33 em_a[20] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[19]/ preq/ ipd b12 c14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 19 output em_d[6]/gp[45] dv dd33 em_a[19] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[18]/ prst/ ipd d11 a14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 18 output em_d[5]/gp[46] dv dd33 em_a[18] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[17]/ad31/ ipd a11 b14 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 17 output em_d[4]/gp[47] dv dd33 em_a[17] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[16]/ pgnt/ ipd c11 b13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 16 output em_d[3]/gp[48] dv dd33 em_a[16] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[15]/ad29/ ipd b11 c13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 15 output em_d[2]/gp[49] dv dd33 em_a[15] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[14]/ad27/ ipd a10 a13 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 14 output em_d[1]/gp[50] dv dd33 em_a[14] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[13]/ad25/ ipd b10 a12 i/o/z for emifa (aem[2:0] = 001), this pin is address bit 13 output em_d[0]/gp[51] dv dd33 em_a[13] if aeaw[2:0] = 100b. this pin is multiplexed between emifa, pci, and gpio. em_a[12]/ pcbe3/ ipd d10 b12 i/o/z gp[89] dv dd33 for emifa, it is address bit 12 output em_a[12]. this pin is multiplexed between emifa, pci, and gpio. em_a[11]/ad24/ ipd c10 c12 i/o/z gp[90] dv dd33 for emifa, it is address bit 11 output em_a[11]. this pin is multiplexed between emifa, pci, and gpio. em_a[10]/ad23/ ipd a9 b11 i/o/z gp[91] dv dd33 for emifa, it is address bit 10 output em_a[10]. this pin is multiplexed between emifa, pci, and gpio. em_a[9]/pidsel/ ipd d9 c11 i/o/z gp[92] dv dd33 for emifa, it is address bit 9 output em_a[9]. this pin is multiplexed between emifa, pci, and gpio. em_a[8]/ad21/ ipd b9 a11 i/o/z gp[93] dv dd33 for emifa, it is address bit 8 output em_a[8]. this pin is multiplexed between emifa, pci, and gpio. em_a[7]/ad22/ ipd c9 c10 i/o/z gp[94] dv dd33 for emifa, it is address bit 7 output em_a[7]. this pin is multiplexed between emifa, pci, and gpio. em_a[6]/ad20/ ipd d8 b10 i/o/z gp[95] dv dd33 for emifa, it is address bit 6 output em_a[6]. this pin is multiplexed between emifa, pci, and gpio. em_a[5]/ad19/ ipd b8 a10 i/o/z gp[96] dv dd33 for emifa, it is address bit 5 output em_a[5]. r0/em_a[4]/gp[10 this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd ]/ a17 b21 i/o/z dv dd33 for emifa, it is address bit 4 output em_a[4]. (aeaw2/pllms2) device overview 30 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between vpbe (venc), emifa, and gpio. b0/lcd_field/ ipd b18 d21 i/o/z em_a[3]/gp[11] dv dd33 for emifa, it is address bit 3 output em_a[3]. b1/em_a[2]/(cle)/ this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd gp[8]/ b16 a20 i/o/z dv dd33 for emifa, it is address bit 2 output em_a[2]. (aeaw0/pllms0) g1/em_a[1]/(ale)/ this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd gp[9]/ a16 b20 i/o/z dv dd33 for emifa, it is address output em_a[1]. (aeaw1/pllms1) this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this is address output em_a[0], which is the least r1/ em_a[0]/ ipd b17 c21 i/o/z significant bit on a 32-bit word address. gp[7]/(aem2) dv dd33 for an 8-bit asynchronous memory, this pin is the 3rd bit of the address. cout0/em_d0/ ipd d16 e21 i/o/z gp[14] dv dd33 cout1/em_d1/ ipd d18 g20 i/o/z gp[15] dv dd33 cout2/em_d2/ ipd d17 e22 i/o/z gp[16] dv dd33 these pins are multiplexed between vpbe (venc), emifa, and cout3/em_d3/ ipd e16 f20 i/o/z gpio. gp[17] dv dd33 cout4/em_d4/ ipd for emifa (aem[2:0] = 001), these pins are the 8-bit bi-directional e18 g21 i/o/z gp[18] dv dd33 data bus (em_d[7:0]). cout5/em_d5/ ipd e17 f22 i/o/z gp[19] dv dd33 cout6/em_d6/ ipd f16 f21 i/o/z gp[20] dv dd33 cout7/em_d7/ ipd f17 h20 i/o/z gp[21] dv dd33 emifa functional pins: 8-bit nand (emifa pinout mode 1, aem[2:0] = 001) this pin is multiplexed between vpbe (venc), emifa (nand), and g1/em_a[1]/(ale)/ gpio. ipd gp[9]/ a16 b20 i/o/z dv dd33 when used for emifa (nand) , this pin is the address latch enable (aeaw1/pllms1) output (ale). this pin is multiplexed between vpbe (venc), emifa (nand), and b1/em_a[2]/(cle)/ gpio. ipd gp[8]/ b16 a20 i/o/z dv dd33 when used for emifa (nand), this pin is the command latch enable (aeaw0/pllms0) output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa (nand), this pin is chip select 2 output em_cs2 for use with nand flash. g0/ em_cs2/ ipd c19 c22 i/o/z this is the chip select for the default boot and rom boot modes. gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. submit documentation feedback device overview 31
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-10. emifa terminal functions (emifa pinout mode 1, aem[2:0] = 001) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa (nand), this pin is chip select 3 output em_cs3 for use lcd_oe/ em_cs3/ ipd with nand flash. c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa (nand), it is chip select 4 output em_cs4 for use with vsync/ em_cs4/ ipd nand flash. e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa (nand), it is chip select 5 output em_cs5 for use with hsync/ em_cs5/ ipd nand flash. f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. cout0/em_d0/ ipd d16 e21 i/o/z gp[14] dv dd33 cout1/em_d1/ ipd d18 g20 i/o/z gp[15] dv dd33 cout2/em_d2/ ipd d17 e22 i/o/z gp[16] dv dd33 these pins are multiplexed between vpbe (venc), emifa (nand), cout3/em_d3/ ipd e16 f20 i/o/z and gpio. gp[17] dv dd33 cout4/em_d4/ ipd for emifa (nand) aem[2:0] = 001, these are the 8-bit bi-directional e18 g21 i/o/z gp[18] dv dd33 data bus (em_d[7:0]). cout5/em_d5/ ipd e17 f22 i/o/z gp[19] dv dd33 cout6/em_d6/ ipd f16 f21 i/o/z gp[20] dv dd33 cout7/em_d7/ ipd f17 h20 i/o/z gp[21] dv dd33 32 device overview submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-11. emifa terminal functions (emifa pinout mode 3, aem[2:0] = 011) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit async/nor with reduced address reach (emifa pinout mode 3, aem[2:0] = 011) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., pcien, aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with asynchronous memories (i.e., nor flash). g0/ em_cs2/ ipd this is the chip select for the default boot and rom boot modes. c19 c22 i/o/z gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with asynchronous memories (i.e., nor flash). lcd_oe/ em_cs3/ ipd c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, it is chip select 4 output em_cs4 for use with asynchronous memories (i.e., nor flash). vsync/ em_cs4/ ipd e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa, and gpiod. for emifa, it is chip select 5 output em_cs5 for use with asynchronous memories (i.e., nor flash). hsync/ em_cs5/ ipd f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between emifa and gpio. em_r/ w/ ipd d13 c17 i/o/z gp[35] dv dd33 for emifa, it is read/write output em_r/ w. em_wait/ ipu for emifa (async/nor), this pin is wait state extension input e15 d20 i/o/z (rdy/ bsy) dv dd33 em_wait. ipu em_oe d15 d19 i/o/z for emifa, it is output enable output em_oe. dv dd33 ipu em_we e14 c19 i/o/z for emifa, it is write enable output em_we. dv dd33 this pin is multiplexed between vpbe (venc), emifa, and gpio. r2/em_ba[0]/ ipd for emifa, this is the bank address 0 output (em_ba[0]). when c17 e20 i/o/z gp[6]/(aem1) dv dd33 connected to an 8-bit asynchronous memory, this pin is the lowest order bit of the byte address. this pin is multiplexed between vpbe (venc), emifa, and gpio. b2/em_ba[1]/ ipd for emifa, this is the bank address 1 output em_ba[1]. when c16 c20 i/o/z gp[5]/(aem0) dv dd33 connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the address. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 33
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-11. emifa terminal functions (emifa pinout mode 3, aem[2:0] = 011) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. em_a[20]/ pinta/ ipd c12 c15 i/o/z em_d[7]/gp[44] dv dd33 em_a[19]/ preq/ ipd b12 c14 i/o/z em_d[6]/gp[45] dv dd33 em_a[18]/ prst/ ipd d11 a14 i/o/z em_d[5]/gp[46] dv dd33 em_a[17]/ad31/ ipd this pin is multiplexed between emifa, pci, and gpio. a11 b14 i/o/z em_d[4]/gp[47] dv dd33 for emifa (aem[2:0] = 011], these pins are the 8-bit bi-directional em_a[16]/ pgnt/ ipd c11 b13 i/o/z bus (em_d[7:0]). em_d[3]/gp[48] dv dd33 em_a[15]/ad29/ ipd b11 c13 i/o/z em_d[2]/gp[49] dv dd33 em_a[14]/ad27/ ipd a10 a13 i/o/z em_d[1]/gp[50] dv dd33 em_a[13]/ad25/ ipd b10 a12 i/o/z em_d[0]/gp[51] dv dd33 this pin is multiplexed between emifa, pci, and gpio. em_a[12]/ pcbe3/ ipd d10 b12 i/o/z gp[89] dv dd33 for emifa, it is address bit 12 output em_a[12]. this pin is multiplexed between emifa, pci, and gpio. em_a[11]/ad24/ ipd c10 c12 i/o/z gp[90] dv dd33 for emifa, it is address bit 11 output em_a[11]. this pin is multiplexed between emifa, pci, and gpio. em_a[10]/ad23/ ipd a9 b11 i/o/z gp[91] dv dd33 for emifa, it is address bit 10 output em_a[10]. this pin is multiplexed between emifa, pci, and gpio. em_a[9]/pidsel/ ipd d9 c11 i/o/z gp[92] dv dd33 for emifa, it is address bit 9 output em_a[9]. this pin is multiplexed between emifa, pci, and gpio. em_a[8]/ad21/ ipd b9 a11 i/o/z gp[93] dv dd33 for emifa, it is address bit 8 output em_a[8]. this pin is multiplexed between emifa, pci, and gpio. em_a[7]/ad22/ ipd c9 c10 i/o/z gp[94] dv dd33 for emifa, it is address bit 7 output em_a[7]. this pin is multiplexed between emifa, pci, and gpio. em_a[6]/ad20/ ipd d8 b10 i/o/z gp[95] dv dd33 for emifa, it is address bit 6 output em_a[6]. this pin is multiplexed between emifa, pci, and gpio. em_a[5]/ad19/ ipd b8 a10 i/o/z gp[96] dv dd33 for emifa, it is address bit 5 output em_a[5]. r0/em_a[4]/gp[10 this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd ]/ a17 b21 i/o/z dv dd33 for emifa, it is address bit 4 output em_a[4]. (aeaw2/pllms2) this pin is multiplexed between vpbe (venc), emifa, and gpio. b0/lcd_field/ ipd b18 d21 i/o/z em_a[3]/gp[11] dv dd33 for emifa, it is address bit 3 output em_a[3]. b1/em_a[2]/(cle)/ this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd gp[8]/ b16 a20 i/o/z dv dd33 for emifa, it is address bit 2 output em_a[2]. (aeaw0/pllms0) g1/em_a[1]/(ale)/ this pin is multiplexed between vpbe (venc), emifa, and gpio. ipd gp[9]/ a16 b20 i/o/z dv dd33 for emifa, it is address output em_a[1]. (aeaw1/pllms1) this pin is multiplexed between vpbe (venc), emifa, and gpio. for emifa, this is address output em_a[0], which is the least r1/ em_a[0]/ ipd b17 c21 i/o/z significant bit on a 32-bit word address. gp[7]/(aem2) dv dd33 for an 8-bit asynchronous memory, this pin is the 3rd bit of the address. emifa functional pins: 8-bit nand (emifa pinout mode 3, aem[2:0] = 011) device overview 34 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-11. emifa terminal functions (emifa pinout mode 3, aem[2:0] = 011) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. this pin is multiplexed between vpbe (venc), emifa (nand), and g1/em_a[1]/(ale)/ gpio. ipd gp[9]/ a16 b20 i/o/z dv dd33 when used for emifa (nand) , this pin is the address latch enable (aeaw1/pllms1) output (ale). this pin is multiplexed between vpbe (venc), emifa (nand), and b1/em_a[2]/(cle)/ gpio. ipd gp[8]/ b16 a20 i/o/z dv dd33 when used for emifa (nand) , this pin is the command latch (aeaw0/pllms0) enable output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with nand flash. g0/ em_cs2/ ipd c19 c22 i/o/z this is the chip select for the default boot and rom boot modes. gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with lcd_oe/ em_cs3/ ipd nand flash. c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 4 output em_cs4 for use with nand vsync/ em_cs4/ ipd flash. e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 5 output em_cs5 for use with nand hsync/ em_cs5/ ipd flash. f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. submit documentation feedback device overview 35
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-11. emifa terminal functions (emifa pinout mode 3, aem[2:0] = 011) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. em_a[13]/ad25/ ipd b10 a12 i/o/z em_d[0]/gp[51] dv dd33 em_a[14]/ad27/ ipd a10 a13 i/o/z em_d[1]/gp[50] dv dd33 em_a[15]/ad29/ ipd b11 c13 i/o/z em_d[2]/gp[49] dv dd33 em_a[16]/ pgnt/ ipd these pins are multiplexed between emifa (nand), pci, and gpio. c11 b13 i/o/z em_d[3]/gp[48] dv dd33 for emifa aem[2:0] = 011 (nand), these pins are the 8-bit em_a[17]/ad31/ ipd a11 b14 i/o/z bi-directional data bus (em_d[7:0]). em_d[4]/gp[47] dv dd33 em_a[18]/ prst/ ipd d11 a14 i/o/z em_d[5]/gp[46] dv dd33 em_a[19]/ preq/ ipd b12 c14 i/o/z em_d[6]/gp[45] dv dd33 em_a[20]/ pinta/ ipd c12 c15 i/o/z em_d[7]/gp[44] dv dd33 device overview 36 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-12. emifa terminal functions (emifa pinout mode 4, aem[2:0] = 100) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit nand (emifa pinout mode 4, aem[2:0] = 100) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., pcien, aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations. this pin is multiplexed between vpbe (venc), emifa (nand), and g1/em_a[1]/(ale)/ gpio. ipd gp[9]/ a16 b20 i/o/z dv dd33 when used for emifa (nand) , this pin is the address latch enable (aeaw1/pllms1) output (ale). this pin is multiplexed between vpbe (venc), emifa (nand), and b1/em_a[2]/(cle)/ gpio. ipd gp[8]/ b16 a20 i/o/z dv dd33 when used for emifa (nand) , this pin is the command latch (aeaw0/pllms0) enable output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with nand flash. g0/ em_cs2/ ipd c19 c22 i/o/z this is the chip select for the default boot and rom boot modes. gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with lcd_oe/ em_cs3/ ipd nand flash. c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 4 output em_cs4 for use with nand vsync/ em_cs4/ ipd flash. e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 5 output em_cs5 for use with nand hsync/ em_cs5/ ipd flash. f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 37
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-12. emifa terminal functions (emifa pinout mode 4, aem[2:0] = 100) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. em_a[13]/ad25/ ipd b10 a12 i/o/z em_d[0]/gp[51] dv dd33 em_a[14]/ad27/ ipd a10 a13 i/o/z em_d[1]/gp[50] dv dd33 em_a[15]/ad29/ ipd b11 c13 i/o/z em_d[2]/gp[49] dv dd33 em_a[16]/ pgnt/ ipd c11 b13 i/o/z these pins are multiplexed between emifa (nand), pci, and gpio. em_d[3]/gp[48] dv dd33 em_a[17]/ad31/ ipd for emifa aem[2:0] = 100 (nand), these pins are the 8-bit a11 b14 i/o/z em_d[4]/gp[47] dv dd33 bi-directional data bus (em_d[7:0]). ci2(ccd10)/ ipd em_a[18]/ prst/ d11 a14 i/o/z dv dd33 em_d[5]/gp[46] em_a[19]/ preq/ ipd b12 c14 i/o/z em_d[6]/gp[45] dv dd33 em_a[20]/ pinta/ ipd c12 c15 i/o/z em_d[7]/gp[44] dv dd33 device overview 38 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-13. emifa terminal functions (emifa pinout mode 5, aem[2:0] = 101) signal type (1) other (2) (3) description zwt zdu name no. no. emifa functional pins: 8-bit nand (emifa pinout mode 5, aem[2:0] = 101) actual pin functions are determined by the pinmux0 and pinmux1 register bit settings (e.g., pcien, aeaw[2:0], aem[2:0], etc.). for more details, see section 3.7 , multiplexed pin configurations. this pin is multiplexed between vpbe (venc), emifa (nand), and g1/em_a[1]/ gpio. ipd (ale)/gp[9]/ a16 b20 i/o/z dv dd33 when used for emifa (nand) , this pin is the address latch enable (aeaw1/pllms1) output (ale). this pin is multiplexed between vpbe (venc), emifa (nand), and b1/em_a[2]/ gpio. ipd (cle)/gp[8]/ b16 a20 i/o/z dv dd33 when used for emifa (nand) , this pin is the command latch (aeaw0/pllms0) enable output (cle). em_wait/ ipu e15 d20 i/o/z when used for emifa (nand), it is ready/busy input (rdy/ bsy). (rdy/ bsy) dv dd33 ipu em_oe d15 d19 i/o/z when used for emifa (nand), this pin is read enable output ( re). dv dd33 ipu em_we e14 c19 i/o/z when used for emifa (nand), this pin is write enable output ( we). dv dd33 this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 2 output em_cs2 for use with nand flash. g0/ em_cs2/ ipd c19 c22 i/o/z this is the chip select for the default boot and rom boot modes. gp[12] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, this pin is chip select 3 output em_cs3 for use with lcd_oe/ em_cs3/ ipd nand flash. c18 d22 i/o/z gp[13] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 4 output em_cs4 for use with nand vsync/ em_cs4/ ipd flash. e19 h22 i/o/z gp[32] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. this pin is multiplexed between vpbe (venc), emifa (nand), and gpio. for emifa, it is chip select 5 output em_cs5 for use with nand hsync/ em_cs5/ ipd flash. f19 j22 i/o/z gp[33] dv dd33 note: this pin features an internal pulldown (ipd). if this pin is connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 39
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-13. emifa terminal functions (emifa pinout mode 5, aem[2:0] = 101) (continued) signal type (1) other (2) (3) description zwt zdu name no. no. cout0/em_d0/ ipd d16 e21 i/o/z gp[14] dv dd33 cout1/em_d1/ ipd d18 g20 i/o/z gp[15] dv dd33 cout2/em_d2/ ipd d17 e22 i/o/z gp[16] dv dd33 these pins are multiplexed between vpbe (venc), emifa (nand), cout3/em_d3/ ipd e16 f20 i/o/z and gpio. gp[17] dv dd33 cout4/em_d4/ ipd for emifa (nand) aem[2:0] = 101, these are the 8-bit bi-directional e18 g21 i/o/z gp[18] dv dd33 data bus (em_d[7:0]). cout5/em_d5/ ipd e17 f22 i/o/z gp[19] dv dd33 cout6/em_d6/ ipd f16 f21 i/o/z gp[20] dv dd33 cout7/em_d7/ ipd f17 h20 i/o/z gp[21] dv dd33 device overview 40 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-14. ddr2 memory controller terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. ddr2 memory controller ddr_clk w7 ab7 i/o/z dv ddr2 ddr2 clock output ddr_clk w8 ab8 i/o/z dv ddr2 ddr2 differential clock output ddr_cke v8 aa8 i/o/z dv ddr2 ddr2 clock enable output ddr_cs t9 y11 i/o/z dv ddr2 ddr2 active low chip select output ddr_we t8 y10 i/o/z dv ddr2 ddr2 active low write enable output ddr_dqm[3] t16 y18 i/o/z dv ddr2 ddr2 data mask outputs dqm3: for upper byte data bus ddr_d[31:24] ddr_dqm[2] t14 y15 i/o/z dv ddr2 dqm2: for ddr_d[23:16] ddr_dqm[1] t6 y7 i/o/z dv ddr2 dqm1: for ddr_d[15:8] dqm0: for lower byte ddr_d[7:0] ddr_dqm[0] t4 y4 i/o/z dv ddr2 ddr_ras u7 y8 i/o/z dv ddr2 ddr2 row access signal output ddr_cas t7 y9 i/o/z dv ddr2 ddr2 column access signal output ddr_dqs[0] u4 aa4 i/o/z dv ddr2 data strobe input/outputs for each byte of the 32-bit data bus. they are outputs to the ddr2 memory when writing and inputs when ddr_dqs[1] u6 aa7 i/o/z dv ddr2 reading. they are used to synchronize the data transfers. ddr_dqs[2] u14 aa15 i/o/z dv ddr2 dqs3 : for upper byte ddr_d[31:24] dqs2: for ddr_d[23:16] dqs1: for ddr_d[15:8] ddr_dqs[3] u16 aa18 i/o/z dv ddr2 dqs0: for bottom byte ddr_d[7:0] ddr_ba[0] u8 aa9 bank select outputs (ba[2:0]). two are required to support 1gb ddr2 ddr_ba[1] v9 ab9 i/o/z dv ddr2 memories. ddr_ba[2] u9 ab10 ddr_a[12] w9 aa10 ddr_a[11] w10 aa11 ddr_a[10] u10 ab11 ddr_a[9] u11 aa12 ddr_a[8] v10 y12 ddr_a[7] v11 ab12 ddr_a[6] w11 aa13 i/o/z dv ddr2 ddr2 address bus output ddr_a[5] w12 y13 ddr_a[4] v12 ab13 ddr_a[3] u12 aa14 ddr_a[2] v13 y14 ddr_a[1] u13 ab14 ddr_a[0] w13 ab15 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) fore more information, see the recommended operating conditions table submit documentation feedback device overview 41
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-14. ddr2 memory controller terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. ddr_d[31] t19 y22 ddr_d[30] u19 aa21 ddr_d[29] v18 y21 ddr_d[28] u18 ab20 ddr_d[27] w17 y20 ddr_d[26] t18 aa20 ddr_d[25] u17 ab19 ddr_d[24] v17 y19 ddr_d[23] t17 aa19 ddr_d[22] v16 ab18 ddr_d[21] w16 ab17 ddr_d[20] u15 y17 ddr_d[19] v15 aa17 ddr_d[18] w15 ab16 ddr_d[17] v14 y16 ddr_d[16] w14 aa16 ddr2 bi-directional data bus can be configured as 32-bits wide or i/o/z dv ddr2 16-bits wide. ddr_d[15] v7 ab6 ddr_d[14] w6 y6 ddr_d[13] v6 aa6 ddr_d[12] w5 ab5 ddr_d[11] v5 y5 ddr_d[10] u5 aa5 ddr_d[9] w4 w5 ddr_d[8] v4 ab4 ddr_d[7] w3 w4 ddr_d[6] v3 ab3 ddr_d[5] u3 y3 ddr_d[4] v2 aa3 ddr_d[3] u2 aa2 ddr_d[2] u1 w2 ddr_d[1] t2 y2 ddr_d[0] t1 y1 ddr_vref t15 w18 i (3) reference voltage input for the sstl_18 i/o buffers ddr_vssdll t13 w15 gnd (3) ground for the ddr2 dll ddr_vdddll t12 w14 s (3) power (1.8 volts) for the ddr2 digital locked loop impedance control for ddr2 outputs. this must be connected via a ddr_zn t10 w12 (3) 200- w resistor to dv ddr2 . impedance control for ddr2 outputs. this must be connected via a ddr_zp t11 w13 (3) 200- w resistor to v ss . device overview 42 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-15. peripheral component interconnect (pci) terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. pci em_a[16]/ pgnt/ ipd this pin is multiplexed between the emifa, pci, and gpio. c11 b13 i/o/z em_d[3]/gp[48] dv dd33 in pci mode, this pin is pci bus grant (i) em_a[18]/ prst/ ipd this pin is multiplexed between the emifa, pci, and gpio. d11 a14 i/o/z em_d[5]/gp[46] dv dd33 in pci mode, this pin is pci reset (i) em_a[19]/ preq/ ipd this pin is multiplexed between the emifa, pci, and gpio. b12 c14 i/o/z em_d[6]/gp[45] dv dd33 in pci mode, this pin is the pci bus request (o/z) em_a[20]/ pinta/ ipd this pin is multiplexed between the emifa, pci, and gpio. c12 c15 i/o/z em_d[7]/gp[44] dv dd33 in pci mode, this pin is the pci interrupt a (o/z) em_a[12]/ pcbe3/ ipd this pin is multiplexed between emifa, pci, and gpio. d10 b12 i/o/z gp[89] dv dd33 in pci mode, this pin is the pci command/byte enable 3 (i/o/z). hd3/vlynq_rxd2/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. b7 b8 i/o/z pcbe2 /gp[61] dv dd33 in pci mode, this pin is the pci command/byte enable 2 (i/o/z) this pin is multiplexed between hpi, ethernet mac (emac), pci, hd11/mtxd3/ ipd c5 a5 i/o/z and gpio. pcbe1/gp[69] dv dd33 in pci mode, this pin is the pci command/byte enable 1 (i/o/z) hrdy/mrxd2/ ipu this pin is multiplexed between hpi, emac, pci, and gpio. d2 c3 i/o/z pcbe0/gp[80] dv dd33 in pci mode, this pin is the pci command/byte enable 0 (i/o/z) em_a[9]/pidsel/ ipd this pin is multiplexed between emifa, pci, and gpio. d9 c11 i/o/z gp[92] dv dd33 in pci mode, this pin is the pci initialization device select (i) vlynq_clock/ ipu this pin is multiplexed between vlynq, pci, and gpio. a7 a8 i/o/z pciclk/gp[57] dv dd33 in pci mode, this pin is the pci clock (i) hd4/vlynq_rxd3/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. c7 c8 i/o/z pframe/gp[62] dv dd33 in pci mode, this pin is the pci frame (i/o/z) hd5/vlynq_txd0/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. a6 a7 i/o/z pirdy/gp[63] dv dd33 in pci mode, this pin is the pci initiator ready (i/o/z) hd6/vlynq_txd1/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. d6 c7 i/o/z ptrdy/gp[64] dv dd33 in pci mode, this pin is the pci target ready (i/o/z) hd7/vlynq_txd2/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. b6 b7 i/o/z pdevsel/gp[65] dv dd33 in pci mode, this pin is the pci device select (i/o/z) hd8/vlynq_txd3/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. a5 a6 i/o/z pperr/gp[66] dv dd33 in pci mode, this pin is the pci parity error (i/o/z) this pin is multiplexed between hpi, ethernet mac (emac), pci, hd9/mcol/ ipd c6 c6 i/o/z and gpio. pstop/gp[67] dv dd33 in pci mode, this pin is the pci stop (i/o/z) hd10/mcrs/ ipd this pin is multiplexed between hpi, emac, pci, and gpio. b5 b6 i/o/z pserr/gp[68] dv dd33 in pci mode, this pin is the pci system error (i/o/z) hd12/mtxd2/ ipd this pin is multiplexed between hpi, emac, pci, and gpio. d5 c5 i/o/z ppar/gp[70] dv dd33 in pci mode, this pin is the pci parity (i/o/z) (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 43
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-15. peripheral component interconnect (pci) terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. em_a[17]/ad31/ ipd a11 b14 i/o/z em_d[4]/gp[47] dv dd33 ipd ad30 e12 d14 i/o/z dv dd33 em_a[15]/ad29/ ipd b11 c13 i/o/z em_d[2]/gp[49] dv dd33 ipd ad28 e11 d13 i/o/z dv dd33 em_a[14]/ad27/ ipd a10 a13 i/o/z em_d[1]/gp[50] dv dd33 ipd ad26 e10 d12 i/o/z dv dd33 em_a[13]/ad25/ ipd b10 a12 i/o/z em_d[0]/gp[51] dv dd33 ipd em_a[11]/ad24/gp[90] c10 c12 i/o/z dv dd33 ipd em_a[10]/ad23/gp[91] a9 b11 i/o/z dv dd33 ipd em_a[7]/ad22/gp[94] c9 c10 i/o/z dv dd33 these pins are multiplexed between pci, emifa, hpi, vlynq, ipd em_a[8]/ad21/gp[93] b9 a11 i/o/z emac (mii), and gpio. dv dd33 for pci, these pins are pci data-address bus [31:0] (i/o/z) ipd em_a[6]/ad20/gp[95] d8 b10 i/o/z dv dd33 ipd em_a[5]/ad19/gp[96] b8 a10 i/o/z dv dd33 hd0/vlynq_scrun/ ipu c8 b9 i/o/z ad18/gp[58] dv dd33 hd2/vlynq_rxd1/ ipd a8 a9 i/o/z ad17/gp[60] dv dd33 hd1/vlynq_rxd0/ ipd d7 c9 i/o/z ad16/gp[59] dv dd33 hd14/mtxd0/ ipd d4 b5 i/o/z ad15/gp[72] dv dd33 hd13/mtxd1/ ipd b4 b4 i/o/z ad14/gp[71] dv dd33 hhwil/mrxdv/ ipd c4 d3 i/o/z ad13/gp[74] dv dd33 hd15/mtxclk/ ipd a4 a4 i/o/z ad12/gp[73] dv dd33 hcntl1/mtxen/ ipd d3 c4 i/o/z ad11/gp[75] dv dd33 44 device overview submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-15. peripheral component interconnect (pci) terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. hcntl0/mrxer/ ipd b3 b2 i/o/z ad10/gp[76] dv dd33 hds2/mrxd0/ ipu c3 c2 i/o/z ad9/gp[78] dv dd33 hr/ w/mrxclk/ ipd a3 a3 i/o/z ad8/gp[77] dv dd33 hds1/mrxd1/ ipu b2 b3 i/o/z ad7/gp[79] dv dd33 hint/mrxd3/ ipu c2 d2 i/o/z ad6/gp[82] dv dd33 these pins are multiplexed between pci, emifa, hpi, vlynq, hcs/mdclk/ ipu c1 d1 i/o/z emac (mii), and gpio. ad5/gp[81] dv dd33 for pci, these pins are pci data-address bus [31:0] (i/o/z) ipd ad4/gp[3] e4 f2 i/o/z dv dd33 has/mdio/ ipu d1 c1 i/o/z ad3/gp[83] dv dd33 ipd ad2/gp[2] e3 f1 i/o/z dv dd33 ipd ad1/gp[1] e2 e2 i/o/z dv dd33 ipd ad0/gp[0] e1 e1 i/o/z dv dd33 submit documentation feedback device overview 45
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-16. emac and mdio terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. emac this pin is multiplexed between hpi, ethernet mac (emac), pci, hcntl1/mtxen/ ipd d3 c4 i/o/z and gpio. ad11/gp[75] dv dd33 in ethernet mac mode, it is transmit enable output mtxen. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd15/mtxclk/ ipd a4 a4 i/o/z and gpio. ad12/gp[73] dv dd33 in ethernet mac mode, it is transmit clock input mtxclk. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd9/mcol/ ipd c6 c6 i/o/z and gpio. pstop/gp[67] dv dd33 in ethernet mac mode, it is collision detect input mcol. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd11/mtxd3/ ipd c5 a5 i/o/z and gpio. pcbe1/gp[69] dv dd33 in ethernet mac mode, it is transmit data 3 output mtxd3. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd12/mtxd2/ ipd d5 c5 i/o/z and gpio. ppar/gp[70] dv dd33 in ethernet mac mode, it is transmit data 2 output mtxd2. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd13/mtxd1/ ipd b4 b4 i/o/z and gpio. ad14/gp[71] dv dd33 in ethernet mac mode, it is transmit data 1 output mtxd1. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd14/mtxd0/ ipd d4 b5 i/o/z and gpio. ad15/gp[72] dv dd33 in ethernet mac mode, it is transmit data 0 output mtxd0. this pin is multiplexed between hpi, ethernet mac (emac), pci, hr/ w/mrxclk/ ipd a3 a3 i/o/z and gpio. ad8/gp[77] dv dd33 in ethernet mac mode, it is receive clock input mrxclk. this pin is multiplexed between hpi, ethernet mac (emac), pci, hhwil/mrxdv/ ipd c4 d3 i/o/z and gpio. ad13/gp[74] dv dd33 in ethernet mac mode, it is receive data valid input mrxdv. this pin is multiplexed between hpi, ethernet mac (emac), pci, hcntl0/mrxer/ ipd b3 b2 i/o/z and gpio. ad10/gp[76] dv dd33 in ethernet mac mode, it is receive error input mrxer. this pin is multiplexed between hpi, ethernet mac (emac), pci, hd10/mcrs/ ipd b5 b6 i/o/z and gpio. pserr/gp[68] dv dd33 in ethernet mac mode, it is carrier sense input mcrs. this pin is multiplexed between hpi, ethernet mac (emac), pci, hint/mrxd3/ ipu c2 d2 i/o/z and gpio. ad6/gp[82] dv dd33 in ethernet mac mode, it is receive data 3 input mrxd3. this pin is multiplexed between hpi, ethernet mac (emac), pci, hrdy/mrxd2/ ipu d2 c3 i/o/z and gpio. pcbe0/gp[80] dv dd33 in ethernet mac mode, it is receive data 2 input mrxd2. this pin is multiplexed between hpi, ethernet mac (emac), pci, hds1/mrxd1/ ipu b2 b3 i/o/z and gpio. ad7/gp[79] dv dd33 in ethernet mac mode, it is receive data 1 input mrxd1. this pin is multiplexed between hpi, ethernet mac (emac), pci, hds2/mrxd0/ ipu c3 c2 i/o/z and gpio. ad9/gp[78] dv dd33 in ethernet mac mode, it is receive data 0 input mrxd0. mdio this pin is multiplexed between hpi, mdio, pci, and gpio. hcs/mdclk/ ipu c1 d1 i/o/z in ethernet mac mode, it is management data clock output ad5/gp[81] dv dd33 mdclk. has/mdio/ ipu this pin is multiplexed between hpi, mdio, pci, and gpio. d1 c1 i/o/z ad3/gp[83] dv dd33 in ethernet mac mode, it is management data i/o mdio (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 46 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-17. vlynq terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. vlynq vlynq_clock/ ipu this pin is multiplexed between vlynq, pci, and gpio. a7 a8 i/o/z pciclk/gp[57] dv dd33 for vlynq, it is the clock vlynq_clock (i/o/z). this pin is multiplexed between hpi, vlynq, pci, and gpio. hd0/vlynq_scrun/ ipu c8 b9 i/o/z for vlynq, it is the serial clock run request vlynq_scrun ad18/gp[58] dv dd33 (i/o/z). hd8/vlynq_txd3/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. a5 a6 i/o/z pperr/gp[66] dv dd33 for vlynq, it is transmit bus bit 3 output vlynq_txd3. hd7/vlynq_txd2/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. b6 b7 i/o/z pdevsel/gp[65] dv dd33 for vlynq, it is transmit bus bit 2 output vlynq_txd2. hd6/vlynq_txd1/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. d6 c7 i/o/z ptrdy/gp[64] dv dd33 for vlynq, it is transmit bus bit 1 output vlynq_txd1. hd5/vlynq_txd0/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. a6 a7 i/o/z pirdy/gp[63] dv dd33 for vlynq, it is transmit bus bit 0 output vlynq_txd0. hd4/vlynq_rxd3/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. c7 c8 i/o/z pframe/gp[62] dv dd33 for vlynq, it is receive bus bit 3 input vlynq_rxd3. hd3/vlynq_rxd2/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. b7 b8 i/o/z pcbe2/gp[61] dv dd33 for vlynq, it is receive bus bit 2 input vlynq_rxd2. hd2/vlynq_rxd1/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. a8 a9 i/o/z ad17/gp[60] dv dd33 for vlynq, it is receive bus bit 1 input vlynq_rxd1. hd1/vlynq_rxd0/ ipd this pin is multiplexed between hpi, vlynq, pci, and gpio. d7 c9 i/o/z ad16/gp[59] dv dd33 for vlynq, it is receive bus bit 0 input vlynq_rxd0. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 47
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-18. host-port interface terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. host-port interface (hpi) hd0/vlynq_scrun/ ipu c8 b9 ad18/gp[58] dv dd33 hd1/vlynq_rxd0/ d7 c9 ad16/gp[59] hd2/vlynq_rxd1/ a8 a9 ad17/gp[60] hd3/vlynq_rxd2/ b7 b8 pcbe2/gp[61] hd4/vlynq_rxd3/ c7 c8 pframe/gp[62] hd5/vlynq_txd0/ a6 a7 pirdy/gp[63] hd6/vlynq_txd1/ d6 c7 ptrdy/gp[64] this pin is multiplexed between hpi, vlynq or emac, pci, hd7/vlynq_txd2/ b6 b7 and gpio. pdevsel/gp[65] i/o/z in hpi mode, these pins are host-port data pins hd[15:0] hd8/vlynq_txd3/ ipd ( i/o/z) and are multiplexed internally with the hpi address a5 a6 pperr/gp[66] dv dd33 lines. hd9/mcol/ c6 c6 pstop/gp[67] hd10/mcrs/ b5 b6 pserr/gp[68] hd11/mtxd3/ c5 a5 pcbe1/gp[69] hd12/mtxd2/ d5 c5 ppar/gp[70] hd13/mtxd1/ b4 b4 ad14/gp[71] hd14/mtxd0/ d4 b5 ad15/gp[72] hd15/mtxclk/ a4 a4 ad12/gp[73] this pin is multiplexed between hpi, emac, pci, and gpio. hhwil/mrxdv/ ipd c4 d3 i/o/z in hpi mode, this pin is half-word identification input hhwil ad13/gp[74] dv dd33 ( i). this pin is multiplexed between hpi, emac, pci, and gpio. in hpi mode, this pin is control input 1 hcntl1 ( i). the state hcntl1/mtxen/ ipd d3 c4 i/o/z of hcntl1 and hcntl0 determines if address, data, or ad11/gp[75] dv dd33 control information is being transmitted between an external host and the dm6433. this pin is multiplexed between hpi, emac, pci, and gpio. in hpi mode, this pin is control input 0 hcntl0 ( i). the state hcntl0/mrxer/ ipd b3 b2 i/o/z of hcntl1 and hcntl0 determines if address, data, or ad10/gp[76] dv dd33 control information is being transmitted between an external host and the dm6433. this pin is multiplexed between hpi, emac, pci, and gpio. hr/ w/mrxclk/ ipd a3 a3 i/o/z in hpi mode, this pin is host read or write select input ad8/gp[77] dv dd33 hr/ w( i). hds2/mrxd0/ ipu this pin is multiplexed between hpi, emac, pci, and gpio. c3 c2 i/o/z ad9/gp[78] dv dd33 in hpi mode, this pin is host data strobe input 2 hds2 ( i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 48 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-18. host-port interface terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. hds1/mrxd1/ ipu this pin is multiplexed between hpi, emac, pci, and gpio. b2 b3 i/o/z ad7/gp[79] dv dd33 in hpi mode, this pin is host data strobe input 1 hds1 ( i). this pin is multiplexed between hpi, emac, pci, and gpio. hrdy/mrxd2/ ipu d2 c3 i/o/z in hpi mode, this pin is host ready output from dsp to host pcbe0/gp[80] dv dd33 ( o/z). this pin is multiplexed between hpi, mdio, pci, and gpio. hcs/mdclk/ ipu c1 d1 i/o/z in hpi mode, this pin is hpi active low chip select input hcs ad5/gp[81] dv dd33 ( i). hint/rxd3/ ipu this pin is multiplexed between hpi, emac, pci, and gpio. c2 d2 i/o/z ad6/gp[82] dv dd33 in hpi mode, this pin is host interrupt output hint ( o/z). this pin is multiplexed between hpi, mdio, pci, and gpio. has/mdio/ ipu in hpi mode, this pin is host address strobe has ( i). d1 c1 i/o/z ad3/gp[83] dv dd33 for proper hpi operation, if this pin is routed out, it must be pulled up via an external resistor. submit documentation feedback device overview 49
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-19. vpbe terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. video out (vpbe) hsync/ em_cs5/ ipd this pin is multiplexed between vpbe, emifa, and gpio. f19 j22 i/o/z gp[33] dv dd33 in vpbe mode, this pin is the vpbe horizontal sync (i/o/z). vsync/ em_cs4/ ipd this pin is multiplexed between vpbe, emifa, and gpio. e19 h22 i/o/z gp[32] dv dd33 in vpbe mode, this pin is the vpbe vertical sync (i/o/z). ipd this pin is multiplexed between vpbe and gpio. vclk/gp[31] d19 g22 i/o/z dv dd33 in vpbe mode, this pin is the vpbe clock output. ipd this pin is multiplexed between vpbe and gpio. vpbeclk/gp[30] g19 k22 i/o/z dv dd33 in vpbe mode, this pin is the vpbe clock input. cout0/em_d[0]/ ipd this pin is multiplexed between vpbe (venc), emifa, and gpio. d16 e21 i/o/z gp[14] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout0. cout1/em_d[1]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. d18 g20 i/o/z gp[15] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout1. cout2/em_d[2]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. d17 e22 i/o/z gp[16] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout2. cout3/em_d[3]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. e16 f20 i/o/z gp[17] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout3. cout4/em_d[4]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. e18 g21 i/o/z gp[18] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout4. cout5/em_d[5]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. e17 f22 i/o/z gp[19] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout5. cout6/em_d[6]/ ipd this pin is multiplexed between vpbe(venc), emifa, and gpio. f16 f21 i/o/z gp[20] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout6. cout7/em_d[7]/ ipd this pin is multiplexed between vpbe (venc), emifa, and gpio. f17 h20 i/o/z gp[21] dv dd33 in vpbe mode, this pin is the video encoder (venc) output cout7. yout0/gp[22]/ ipd f18 j20 i/o/z (bootmode0) dv dd33 yout1/gp[23]/ ipd f15 k20 i/o/z (bootmode1) dv dd33 yout2/gp[24]/ ipd these pins are multiplexed between vpbe (venc) and gpio. g15 l20 i/o/z (bootmode2) dv dd33 after reset, these are video encoder (venc) outputs 6:0, yout[6:0]. yout3/gp[25]/ ipd for proper dm6433 device operation, the yout6 pin must be pulled g16 h21 i/o/z (bootmode3) dv dd33 down via an external resistor. for proper dm6433 device operation, the yout5 pin must be pulled yout4/gp[26]/ ipd g17 k19 i/o/z up via an external resistor. (fastboot) dv dd33 ipu yout5/gp[27] h17 l19 i/o/z dv dd33 yout6/ ipd h16 j21 i/o/z gp[28] dv dd33 yout7/ ipd this pin is multiplexed between vpbe (venc) and gpio. h15 k21 i/o/z gp[29] dv dd33 in vpbe mode, this pin is the venc output 7, yout7. lcd_oe/ em_cs3/ ipd this pin is multiplexed between vpbe, emifa, and gpio. c18 d22 i/o/z gp[13] dv dd33 in vpbe mode, it is the lcd output enable lcd_oe (o/z). this pin is multiplexed between vpbe, emifa, and gpio. g0/ em_cs2/ ipd c19 c22 i/o/z in vpbe mode, this pin is the rgb666/888 green output data bit 0, gp[12] dv dd33 g0. this pin is multiplexed between vpbe, emifa, and gpio. b0/lcd_field/ ipd b18 d21 i/o/z in vpbe mode, this pin is the rgb666/888 blue output data bit 0, b0 em_a[3]/gp[11] dv dd33 or lcd interlaced lcd_field (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 50 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-19. vpbe terminal functions (continued) signal type (1) other (2) (3) description zwt zdu name no. no. r0/em_a[4]/ ipd this pin is multiplexed between vpbe, emifa, and gpio. gp[10]/ a17 b21 i/o/z dv dd33 in vpbe mode, this pin is the rgb666/888 red output data bit 0, r0. (aeaw2/pllms2) g1/em_a[1]/ this pin is multiplexed between vpbe, emifa, and gpio. ipd (ale)/gp[9]/ a16 b20 i/o/z in vpbe mode, this pin is the rgb666/888 green output data bit 1, dv dd33 (aeaw1/pllms1) g1. b1/em_a[2]/ this pin is multiplexed between vpbe, emifa, and gpio. ipd (cle)/gp[8]/ b16 a20 i/o/z in vpbe mode, this pin is the rgb666/888 blue output data bit 1, dv dd33 (aeaw0/pllms0) b1. r1/em_a[0]/ ipd this pin is multiplexed between vpbe, emifa, and gpio. b17 c21 i/o/z gp[7]/(aem2) dv dd33 in vpbe mode, this pin is the rgb666/888 red output data bit 1, r1. r2/em_ba[0]/ ipd this pin is multiplexed between vpbe, emifa, and gpio. c17 e20 i/o/z gp[6]/(aem1) dv dd33 in vpbe mode, this pin is the rgb666/888 red output data bit 2, r2. this pin is multiplexed between vpbe, emifa, and gpio. b2/em_ba[1]/ ipd c16 c20 i/o/z in vpbe mode, this pin is the rgb666/888 blue output data bit 2, gp[5]/(aem0) dv dd33 b2. submit documentation feedback device overview 51
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-20. dac [part of vpbe] terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. dac[a:d] reference voltage input (0.5 v) dac_vref n19 v22 a i (3) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . output of dac a dac_iout_a p19 v21 a o note: if the dac peripheral is not being used, for proper device operation, this pin must be left unconnected. output of dac b dac_iout_b p18 u22 a o note: if the dac peripheral is not being used, for proper device operation, this pin must be left unconnected. output of dac c dac_iout_c n18 t21 a o note: if the dac peripheral is not being used, for proper device operation, this pin must be left unconnected. output of dac d dac_iout_d n17 t22 a o note: if the dac peripheral is not being used, for proper device operation, this pin must be left unconnected. 1.8 v analog i/o power v dda_1p8v p17 v20 s (3) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . analog i/o ground v ssa_1p8v p16 u20 gnd (3) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . 1.20 v analog core supply voltage (-7/-6/-5/-4/-l/-q6/-q5/-q4 devices) 1.05 v analog core supply voltage v dda_1p1v n15 t20 s (3) (-7/-6/-5/-4/-l/-q5 devices) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . analog core ground v ssa_1p1v p15 t19 gnd (3) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . external resistor connection for current bias configuration. this must be connected via a 4 k w resistor to v ssa_1p8v . dac_rbias n16 u21 a i (3) note: if the dac peripheral is not being used, for proper device operation, this pin must be tied directly to v ss . (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) specifies the operating i/o supply voltage for each signal (3) for more information, see the recommended operating conditions table device overview 52 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-21. i2c terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. i2c for i2c, this pin is i2c clock. in i2c master mode, this pin is an output. in i2c slave mode, this pin is an input. scl m2 n2 i/o/z dv dd33 when the i2c module is used, for proper device operation, this pin must be pulled up via an external resistor. for i2c, this pin is the i2c bi-directional data signal. sda m3 p2 i/o/z dv dd33 when the i2c module is used, for proper device operation, this pin must be pulled up via an external resistor. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 53
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-22. multichannel buffered serial port 0 (mcbsp0) terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. multichannel buffered serial port 0 (mcbsp0) for more details on pin multiplexing, see section 3.7 , multiplexed pin configurations. clks0/tout0l/ ipd this pin is multiplexed between mcbsp0, timer0, and gpio. j4 l3 i/o/z gp[97] dv dd33 for mcbsp0, it is mcbsp0 external clock source (i). aclkr0/clkx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h1 j1 i/o/z gp[99] dv dd33 for mcbsp0, it is mcbsp0 transmit clock clkx0 (i/o/z). ahclkr0/clkr0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. j2 k1 i/o/z gp[101] dv dd33 for mcbsp0, it is mcbsp0 receive clock clkr0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[2]/fsx0/ ipd h3 j2 i/o/z for mcbsp0, it is mcbsp0 transmit frame synchronization fsx0 gp[103] dv dd33 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[3]/fsr0/ ipd g4 j3 i/o/z for mcbsp0, it is mcbsp0 receive frame synchronization fsr0 gp[102] dv dd33 (i/o/z). axr0[1]/dx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. j3 k2 i/o/z gp[104] dv dd33 for mcbsp0, it is mcbsp0 data transmit output dx0 (o/z). afsr0/dr0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h4 k3 i/o/z gp[100] dv dd33 for mcbsp0, it is mcbsp0 data receive input dr0 (i). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 54 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-23. multichannel audio serial port (mcasp0) terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. mcasp0 amutein0/ ipd this pin is multiplexed between mcasp0 and gpio. f2 g3 i/o/z gp[109] dv dd33 for mcasp0, it is mcasp0 mute input amutein0 (i). ipd this pin is multiplexed between mcasp0 and gpio. amute0/gp[110] g3 h3 i/o/z dv dd33 for mcasp0, it is mcasp0 mute output amute0 (o/z). aclkr0/clkx0/ ipd this pin is multiplexed between mcasp0, mcbsp0, and gpio. h1 j1 i/o/z gp[99] dv dd33 for mcasp0, it is mcasp0 receive bit clock aclkr0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. ahclkr0/clkr0/ ipd j2 k1 i/o/z for mcasp0, it is mcasp0 receive high-frequency master clock gp[101] dv dd33 ahclkr0 (i/o/z). ipd this pin is multiplexed between mcasp0 and gpio. aclkx0/gp[106] f1 g1 i/o/z dv dd33 for mcasp0, it is mcasp0 transmit bit clock aclkx0 (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd ahclkx0/gp[108] g1 h1 i/o/z for mcasp0, it is mcasp0 transmit high-frequency master clock dv dd33 ahclkx0 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. afsr0/dr0/ ipd h4 k3 i/o/z for mcasp0, it is mcasp0 receive frame synchronization afsr0 gp[100] dv dd33 (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd afsx0/gp[107] g2 g2 i/o/z for mcasp0, it is mcasp0 transmit frame synchronization afsx0 dv dd33 (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[3]/fsr0/ ipd g4 j3 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 3 gp[102] dv dd33 axr0[3] (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[2]/fsx0/ ipd h3 j2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 2 gp[103] dv dd33 axr0[2] (i/o/z). this pin is multiplexed between mcasp0, mcbsp0, and gpio. axr0[1]/dx0/ ipd j3 k2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 1 gp[104] dv dd33 axr0[1] (i/o/z). this pin is multiplexed between mcasp0 and gpio. ipd axr0[0]/gp[105] h2 h2 i/o/z for mcasp0, it is mcasp0 transmit/receive (tx/rx) data pin 0 dv dd33 axr0[0] (i/o/z). (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 55
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-24. uart0 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. uart0 urxd0/ ipu this pin is multiplexed between uart0 (data) and gpio. l2 m2 i/o/z gp[85] dv dd33 when used by uart0 this pin is the receive data input urxd0. utxd0/ ipu this pin is multiplexed between uart0 (data) and gpio. k3 n1 i/o/z gp[86] dv dd33 in uart0 mode, this pin is the transmit data output utxd0. ucts0 ipu this pin is multiplexed between the uart0 (flow control) and gpio. l1 p1 i/o/z gp[87] dv dd33 in uart0 mode, this pin is the clear to send input ucts0. urts0 this pin is multiplexed between the uart0 (flow control), pwm0, ipu pwm0 l3 m3 i/o/z and gpio. dv dd33 gp[88] in uart0 mode, this pin is the ready to send output urts0. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 56 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-25. pwm0, pwm1, and pwm2 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. pwm2 this pin is multiplexed between the system clock generator (pll1), clkout0/pwm2/ ipd m1 r1 i/o/z pwm2, and gpio. gp[84] dv dd33 for pwm2, this pin is output pwm2. pwm1 ipd this pin is multiplexed between gpio and pwm1. gp[4]/pwm1 f3 f3 i/o/z dv dd33 for pwm1, this pin is output pwm1. pwm0 this pin is multiplexed between the uart0 (flow control), pwm0, urts0/pwm0/ ipu l3 m3 i/o/z and gpio. gp[88] dv dd33 for pwm0, this pin is output pwm0. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 57
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-26. timer 0, timer 1, and timer 2 terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. timer 2 no external pins. the timer 2 (watchdog) peripheral pins are not pinned out as external pins. timer 1 this pin is multiplexed between the timer 1 and gpio. tinp1l/ ipu l4 p3 i/o/z for timer 1, this pin is the timer 1 input pin for the lower 32-bit gp[56] dv dd33 counter this pin is multiplexed between the timer 1 and gpio. tout1l/ ipu k4 n3 i/o/z for timer 1, this pin is the timer 1 output pin for the lower 32-bit gp[55] dv dd33 counter timer 0 this pin is multiplexed between the timer 0 and gpio. tinp0l/ ipd k2 l2 i/o/z for timer 0, this pin is the timer 0 input pin for the lower 32-bit gp[98] dv dd33 counter clks0/ this pin is multiplexed between the mcbsp0, timer 0, and gpio. ipd tout0l/ j4 l3 i/o/z for timer 0, this pin is the timer 0 output pin for the lower 32-bit dv dd33 gp[97] counter (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 58 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-27. gpio terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. gpio 100 out of 111 gpio pins on the dm6433 device are multiplexed with other peripherals pin functions (e.g., vpbe, pci, hpi, vlynq, emac/mdio, mcasp0, mcbsp0, timer 0, timer 1, uart0, pwm0, pwm1, pwm2, emifa, and the clkout0 pin), see the peripheral-specific terminal functions tables for the gpio multiplexing. (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 59
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-28. standalone gpio 3.3 v terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. standalone gpio 3.3 v ipd gp[36] c15 b19 i/o/z this pin functions as standalone gpio pin 36. dv dd33 ipd gp[37] b15 b18 i/o/z this pin functions as standalone gpio pin 37. dv dd33 ipd gp[38] c14 b17 i/o/z this pin functions as standalone gpio pin 38. dv dd33 ipd gp[39] b14 a16 i/o/z this pin functions as standalone gpio pin 39. dv dd33 ipd gp[40] d14 c18 i/o/z this pin functions as standalone gpio pin 40. dv dd33 ipd gp[41] c13 b16 i/o/z this pin functions as standalone gpio pin 41. dv dd33 ipd gp[42] b13 b15 i/o/z this pin functions as standalone gpio pin 42. dv dd33 ipd gp[43] a12 a15 i/o/z this pin functions as standalone gpio pin 43. dv dd33 ipd gp[52] a15 a19 i/o/z this pin functions as standalone gpio pin 52. dv dd33 ipd gp[53] a13 a17 i/o/z this pin functions as standalone gpio pin 53. dv dd33 ipd gp[54] a14 a18 i/o/z this pin functions as standalone gpio pin 54. dv dd33 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal device overview 60 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-29. reserved terminal functions signal type (1) other (2) (3) description zwt zdu name no. no. reserved rsv1 e5 d4 reserved. (leave unconnected, do not connect to power or ground) rsv2 k5 l4 reserved. (leave unconnected, do not connect to power or ground) rsv3 l5 m4 reserved. (leave unconnected, do not connect to power or ground) rsv4 l15 p19 reserved. (leave unconnected, do not connect to power or ground) rsv5 r13 w16 reserved. (leave unconnected, do not connect to power or ground) (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal (2) ipd = internal pulldown, ipu = internal pullup. for more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. (3) specifies the operating i/o supply voltage for each signal submit documentation feedback device overview 61
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-30. supply terminal functions signal type (1) other description zwt zdu name no. no. supply voltage pins a1 a2 a2 a21 a18 b1 e6 d6 e8 d8 f5 d10 f7 d16 f9 d18 f11 e3 f13 e5 g6 e7 g8 e9 g10 e11 g12 e13 g14 e15 h5 e17 h18 e19 j1 f4 j6 f18 j14 g5 3.3 v i/o supply voltage dv dd33 s (see the power-supply decoupling section of this data manual) j16 g19 k15 h4 k17 h18 l6 j5 m5 j19 m15 k4 n6 k18 p1 l1 l5 l21 m18 m20 n5 n19 p4 p18 p20 p22 r5 t4 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal device overview 62 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-30. supply terminal functions (continued) signal type (1) other description zwt zdu name no. no. l14 u5 p5 v1 p7 v4 p9 v6 p11 v8 p13 v10 r4 v12 r6 v14 r8 v16 1.8 v ddr2 i/o supply voltage dv ddr2 s (see the power-supply decoupling section of this data manual) r10 v18 r12 w7 r14 w9 r16 w11 t5 w17 v1 w19 w18 aa1 w19 ab21 ab22 h7 j10 h9 j11 h11 j12 h13 j13 j8 k9 j10 k14 j12 l9 k7 l13 k9 l14 k11 m9 1.20 v supply voltage (-7/-6/-5/-4/-l/-q6/-q5/-q4 devices) cv dd k13 m10 s 1.05 v core supply voltage (-7/-6/-5/-4/-l/-q5 devices) (see the power-supply decoupling section of this data manual) l8 m14 l10 n9 l12 n14 m7 p10 m9 p11 m11 p12 m13 p13 n8 n10 n12 submit documentation feedback device overview 63
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 2-31. ground terminal functions signal type (1) other description zwt zdu name no. no. ground pins a19 a1 b1 a22 b19 b22 e7 d5 e9 d7 e13 d9 f4 d11 f6 d15 f8 d17 f10 e4 f12 e6 f14 e8 g5 e10 g7 e12 g9 e14 g11 e16 g13 e18 g18 f5 h6 f19 v ss h8 g4 gnd ground pins h10 g18 h12 h5 h14 h19 h19 j4 j5 j9 j7 j14 j9 j18 j11 k5 j13 k10 j15 k11 j17 k12 j18 k13 k1 l10 k6 l11 k8 l12 k10 l18 k12 l22 k14 m1 k16 m5 (1) i = input, o = output, z = high impedance, s = supply voltage, gnd = ground, a = analog signal 64 device overview submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 2-31. ground terminal functions (continued) signal type (1) other description zwt zdu name no. no. l7 m11 l9 m12 l11 m13 l13 m19 l17 n4 l19 n10 m6 n11 m8 n12 m10 n13 m12 n18 m14 p5 m16 p9 m17 p14 m18 p21 m19 r4 n5 r18 n7 r19 n9 r20 n11 r21 n13 r22 n14 t5 v ss p6 t18 gnd ground pins p8 u4 p10 u18 p12 u19 p14 v5 r1 v7 r5 v9 r7 v11 r9 v13 r11 v15 r15 v17 r17 v19 r18 w1 r19 w6 v19 w8 w1 w10 w2 w20 w21 w22 aa22 ab1 ab2 submit documentation feedback device overview 65
2.7 device support 2.7.1 development support 2.8 device and development-support tool nomenclature tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com ti offers an extensive line of development tools for the tms320dm643x dmp platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the tool's support documentation is electronically available within the code composer studio? integrated development environment (ide). the following products support development of tms320dm643x dmp-based applications: software development tools: code composer studio? integrated development environment (ide): including editor c/c++/assembly code generation, and debug plus additional development tools scalable, real-time foundation software (dsp/bios?), which provides the basic run-time target software needed to support any soc application. hardware development tools: extended development system (xds?) emulator (supports tms320dm643x dmp multiprocessor system debug) evm (evaluation module) for a complete listing of development-support tools for the tms320dm643x dmp platform, visit the texas instruments web site on the worldwide web at http://www.ti.com uniform resource locator (url). for information on pricing and availability, contact the nearest ti field sales office or authorized distributor. to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all dsp devices and support tools. each dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tms320dm6433zwtq6). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/tmdx) through fully qualified production devices/tools (tms/tmds). device development evolutionary flow: tmx experimental device that is not necessarily representative of the final device's electrical specifications. tmp final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. tms fully-qualified production device. support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product. tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. device overview 66 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 predictions show that prototype devices (tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, zwt), the temperature range (for example, "blank" is the commercial temperature range), and the device speed range in megahertz (for example, "6" indicates [600-mhz]). figure 2-10 provides a legend for reading the complete device name for any tms320dm643x dmp platform member. figure 2-10. device nomenclature submit documentation feedback device overview 67 c64x+? dsp: dm6437dm6435 dm6433 dm6431 prefix tms 320 dm6433 zwt tmx = experimental devicetms = qualified device device family 320 = tms320? dsp family package type(a) zwt = 361-pin plastic bga, with pb-free soldered balls zdu = 376-pin plastic bga, with pb-free soldered balls [green] device a. bga = ball grid array b. for tmx initial devices, the device number is dm6437. c. not all combinations are available. for more information, see the table in the packing information section. d. the maximum cpu frequency for the -q6 device is 660 mhz. see the section for maximum operating frequencies of the pll1 controller. orderable devices pll1 and pll2 e. the device speed range symbolization indicates the maximum cpu frequency when the core voltage (cv ) is set to 1.2 v. to determine the maximum cpu frequency the core voltage is set to 1.05v, refer to the section. dd pll1 and pll2 device speed range ( ) 4 = 400 mhz5 = 500 mhz 6 = 600 mhz 7 = 700 mhz l = low power device (d) temperature range (junction) ( ) ( ) silicon revision: blank = revision 1.3 blank = 0 c to 90 c, commercial grade q = -40c to 125c, automotive grade r = 0 c to 90 c, commercial grade (tape and reel) s = -40c to 125c, automotive grade (tape and reel)
2.9 documentation support 2.9.1 related documentation from texas instruments tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the following documents describe the tms320dm643x digital media processor (dmp). copies of these documents are available on the internet at www.ti.com . tip: enter the literature number in the search box provided at www.ti.com. the current documentation that describes the dm643x dmp, related peripherals, and other technical collateral, is available in the c6000 dsp product folder at: www.ti.com/c6000 . spru978 tms320dm643x dmp dsp subsystem reference guide. describes the digital signal processor (dsp) subsystem in the tms320dm643x digital media processor (dmp). spru983 tms320dm643x dmp peripherals overview reference guide. provides an overview and briefly describes the peripherals available on the tms320dm643x digital media processor (dmp). spraa84 tms320c64x to tms320c64x+ cpu migration guide. describes migrating from the texas instruments tms320c64x digital signal processor (dsp) to the tms320c64x+ dsp. the objective of this document is to indicate differences between the two cores. functionality in the devices that is identical is not included. spru732 tms320c64x/c64x+ dsp cpu and instruction set reference guide. describes the cpu architecture, pipeline, instruction set, and interrupts for the tms320c64x and tms320c64x+ digital signal processors (dsps) of the tms320c6000 dsp family. the c64x/c64x+ dsp generation comprises fixed-point devices in the c6000 dsp platform. the c64x+ dsp is an enhancement of the c64x dsp with added functionality and an expanded instruction set. spru871 tms320c64x+ dsp megamodule reference guide. describes the tms320c64x+ digital signal processor (dsp) megamodule. included is a discussion on the internal direct memory access (idma) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. device overview 68 submit documentation feedback
3 device configurations 3.1 system module registers tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the system module includes status and control registers required for configuration of the device. brief descriptions of the various registers are shown in table 3-1 . system module registers required for device configurations are discussed in the following sections. table 3-1. system module register memory map hex address range register acronym description 0x01c4 0000 pinmux0 pin multiplexing control 0 (see section 3.7.2.1 , pinmux0 register description). 0x01c4 0004 pinmux1 pin multiplexing control 1 (see section 3.7.2.2 , pinmux1 register description). 0x01c4 0008 dspbootaddr dsp boot address (see section 3.4.2.3 , dspbootaddr register). 0x01c4 000c bootcmplt boot complete (see section 3.4.2.2 , bootcmplt register). 0x01c4 0010 ? reserved 0x01c4 0014 bootcfg device boot configuration (see section 3.4.2.1 , bootcfg register). 0x01c4 0018 - 0x01c4 0027 ? reserved 0x01c4 0028 jtagid jtag id (see section 6.23.1 , jtag id (jtagid) register description(s)). 0x01c4 002c ? reserved 0x01c4 0030 hpictl hpi control (see section 3.6.2.1 , hpi control register). 0x01c4 0034 ? reserved 0x01c4 0038 ? reserved 0x01c4 003c mstpri0 bus master priority control 0 (see section 3.6.1 , switch central resource (scr) bus priorities). 0x01c4 0040 mstpri1 bus master priority control 1 (see section 3.6.1 , switch central resource (scr) bus priorities). 0x01c4 0044 vpss_clkctl vpss clock control (see section 3.3.1.2.1 , vpss clocks). 0x01c4 0048 vdd3p3v_pwdn v dd 3.3-v i/o powerdown control (see section 3.2 , power considerations). 0x01c4 004c ddrvtper ddr2 vtp enable register (see section 6.9.4 , ddr2 memory controller). 0x01c4 0050 - 0x01c4 0080 ? reserved 0x01c4 0084 timerctl timer control (see section 3.6.2.2 , timer control register). 0x01c4 0088 edmatccfg edma transfer controller default burst size configuration (see section 3.6.2.3 , edma tc configuration register). 0x01c4 008c ? reserved submit documentation feedback device configurations 69
3.2 power considerations tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dm6433 provides several means of managing power consumption. as described in the section 6.3.4 , dm6433 power and clock domains, the dm6433 has one single power domain?the ?always on? power domain. within this power domain, the dm6433 utilizes local clock gating via the power and sleep controller (psc) to achieve power savings. for more details on the psc, see section 6.3.5 , power and sleep controller (psc) and the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). some of the dm6433 peripherals support additional power saving features. for more details on power saving features supported, see the peripheral-specific reference guides [listed/linked in the tms320dm643x dmp peripherals overview reference guide (literature number spru983 ). most dm6433 3.3-v i/os can be powered-down to reduce power consumption. the vdd3p3v_pwdn register in the system module (see figure 3-1 ) is used to selectively power down unused 3.3-v i/o pins. for independent control, the 3.3-v i/os are separated into functional groups?most of which are named according to the pin multiplexing groups (see table 3-2 ). for these i/o groups, only the i/o buffers needed for host/emifa boot or power-up operations are powered up by default (clkout block, emifa/vpss block, host block, pci data block, and gpio block). note: to save power, all other i/o buffers are powered down by default. before using these pins, the user must program the vdd3p3v_pwdn register to power up the corresponding i/o buffers. for a list of multiplexed pins on the device and the pin mux group each pin belongs to, see section 3.7.3.1 , multiplexed pins on dm6433. note: the vdd3p3v_pwdn register only controls the power to the i/o buffers. the power and sleep controller (psc) determines the clock/power state of the peripheral. 31 16 reserved r-0000 0000 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pcidat embk3 ur0fc ur0dat timer1 timer0 sp pwm1 gpio host embk2 embk1 embk0 clkout r-00 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r/w = read/write; r = read only; - n = value after reset figure 3-1. vdd3p3v_pwdn register? 0x01c4 0048 device configurations 70 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-2. vdd3p3v_pwdn register descriptions (1) bit name description 31:14 reserved reserved. read-only, writes have no effect. pci data block i/o power down control. controls the power of the 3 i/o pins in the pci data block. 13 pcidat 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 3 i/o power down control. controls the power of the 8 i/o pins in the emifa/vpss sub-block 3. 12 embk3 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). uart0 flow control block i/o power down control. controls the power of the 2 i/o pins in the uart0 flow control block. 11 ur0fc 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. uart0 data block i/o power down control. controls the power of the 2 i/o pins in the uart0 data block. 10 ur0dat 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. timer1 block i/o power down control. controls the power of the 2 i/o pins in the timer1 block. 9 timer1 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. timer0 block i/o power down control. controls the power of the 2 i/o pins in the timer0 block. 8 timer0 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. serial port block i/o power down control. controls the power of the 12 i/o pins in the serial port block (serial port sub-block 0 and serial port sub-block 1). 7 sp 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. pwm1 block i/o power down control. contros thel power of the 1 i/o pin in the pwm1 block. 6 pwm1 0 = i/o pins powered up. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z) [ default]. gpio block i/o power down control. controls the power of the 4 i/o pins in the gpio block. 5 gpio 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). host block i/o power down control. controls the power of the 27 i/o pins in the host block. 4 host 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 2 i/o power down control. controls the power of the 3 i/o pins in the emifa/vpss sub-block 2. 3 embk2 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). (1) for more details on i/o pins belonging to each pin mux block, see section 3.7 , multiplexed pin configurations. submit documentation feedback device configurations 71
3.3 clock considerations 3.3.1 clock configurations after device reset 3.3.1.1 device clock frequency tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-2. vdd3p3v_pwdn register descriptions (continued) bit name description emifa/vpss sub-block 1 i/o power down control. controls the power of the 29 i/o pins in the emifa/vpss sub-block 1. 2 embk1 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). emifa/vpss sub-block 0 i/o power down control. controls the power of the 21 i/o pins in the emifa/vpss sub-block 0. 1 embk0 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). clkout block i/o power down control. controls the power of the 1 i/o pin in the clkout block. 0 clkout 0 = i/o pins powered up [ default]. 1 = i/o pins powered down and not operational. outputs are 3-stated ( hi-z). global device and local peripheral clocks are controlled by the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc). in addition, the system module vpss_clkctl register configures the clock source to the video processing subsystem (vpss). after device reset, the user is responsible for programming the pll controllers (pllc1 and pllc2) and the power and sleep controller (psc) to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). for additional power savings, some of the dm6433 peripherals support clock gating within the peripheral boundary. for more details on clock gating and power saving features supported by a specific peripheral, see the peripheral-specific reference guides [listed/linked in the tms320dm643x dmp peripherals overview reference guide (literature number spru983 )]. the dm6433 defaults to pll bypass mode. to bring the device up to the desired clock frequency, the user should program pllc1 and pllc2 after device reset. dm6433 supports a fastboot option, where upon exit from device reset the internal bootloader code automatically programs the pllc1 into pll mode with a specific pll multiplier and divider to speed up device boot. while the fastboot option is beneficial for faster boot, the pll multiplier and divider selected for boot may not be the exact frequency desired for the run-time application. it is the user's responsibility to reconfigure pllc1 after fastboot to bring the device into the desired clock frequency. section 3.4.1 , boot modes discusses the different fast boot modes in more detail. the user must adhere to the various clock requirements when programming the pllc1 and pllc2: fixed frequency ratio requirements between clkdiv1, clkdiv3, and clkdiv6 clock domains. for more details on the frequency ratio requirements, see section 6.3.4 , dm6433 power and clock domains. pll multiplier and frequency ranges. for more details on pll multiplier and frequency ranges, see section 6.7.1 , pll1 and pll2. device configurations 72 submit documentation feedback
3.3.1.2 module clock state tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the clock and reset state for each of the modules is controlled by the power and sleep controller (psc). table 3-3 shows the default state of each module after a device-level global reset. the dm6433 device has four different module states?enable, disable, syncreset, or swrstdisable. for more information on the definitions of the module states, the psc, and psc programming, see section 6.3.5 , power and sleep controller (psc) and the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). table 3-3. dm6433 default module states default module state lpsc # module name [psc register mdstatn.state] 0 vpss (master) swrstdisable 1 vpss (slave) swrstdisable 2 edmacc swrstdisable 3 edmatc0 swrstdisable 4 edmatc1 swrstdisable 5 edmatc2 swrstdisable 6 emac memory controller swrstdisable 7 mdio swrstdisable 8 emac swrstdisable 9 mcasp0 swrstdisable 11 vlynq swrstdisable 12 hpi swrstdisable 13 ddr2 memory contoller swrstdisable swrstdisable, if configuration pins aem[2:0] = 000b 14 emifa enable, if configuration pins aem[2:0] = others [001b, 011b, 100b, and 101b] 15 pci swrstdisable 16 mcbsp0 swrstdisable 18 i2c swrstdisable 19 uart0 swrstdisable 23 pwm0 swrstdisable 24 pwm1 swrstdisable 25 pwm2 swrstdisable 26 gpio swrstdisable 27 timer0 swrstdisable 28 timer1 swrstdisable 39 c64x+ cpu enable submit documentation feedback device configurations 73
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com 3.3.1.2.1 vpss clocks the video processing subsystem (vpss) clocks are controlled via the vpss_clkctl register. the vpss_clkctl register format is shown in figure 3-2 and the bit field descriptions are given in table 3-4 . 31 16 reserved r-0000 0000 0000 0000 15 5 4 3 2 1 0 dac ven reserved rsv muxsel clken clken r-0000 0000 000 r/w-0 r/w-0 r/w-0 r/w-00 legend: r = read; w = write; - n = value after reset figure 3-2. vpss_clkctl register? 0x01c4 0044 table 3-4. vpss_clkctl register bit description bit name description 31:5 reserved reserved. read-only, writes have no effect. video dac clock enable. 4 dacclken 0 = dac clock disabled [ default]. 1 = dac clock enabled. video encoder clock enable. 3 venclken 0 = venc clock disabled [ default]. 1 = venc clock enabled. 2 rsv reserved. for proper device operation, the user must write 0 to this bit. vpbe (video encoder and dac) clock selection setting venc clk dac clk 00 [ default] 27 mhz (a) 27 mhz (a) 01 54 mhz (b) 54 mhz (b) 1:0 muxsel (1) (2) 10 vpbeclk input vpbeclk input 11 reserved reserved (a) the 27-mhz clock comes from pllc1 sysclkbp. (b) the 54-mhz clock comes from pllc2 pll2_sysclk2. (1) muxsel = 00 selects pllc1 sysclkbp as the clock source to the vpbe. the pllc1 sysclkbp is a 27-mhz clock if the following settings are true: a. mxi/clkin clock source is 27 mhz. b. pllc1 bypass divider register (bpdiv) is left at the default setting of divide-by-1. (2) muxsel = 01 selects pllc2 pll2_sysclk2 as the clock source to the vpbe. the pllc2 pll2_sysclk2 is a 54-mhz clock if the following settings are true: a. mxi/clkin clock source is 27 mhz. b. pllc2 is in pll mode with multiplier x20 to generate a pll output clock of 27 mhz x 20 = 540 mhz. c. plldiv2.ratio is left at the default setting of divide-by-10 to generate sysclk2 = 54 mhz. for more details on the different methods and software sequence to clock (gate) the vpbe components, see the tms320dm643x dmp video processing back end (vpbe) user?s guide (literature number spru952 ). 74 device configurations submit documentation feedback
3.4 boot sequence 3.4.1 boot modes tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the boot sequence is a process by which the device's memory is loaded with program and data sections, and by which some of the device's internal registers are programmed with predetermined values. the boot sequence is started automatically after each device-level global reset. for more details on device-level global resets, see section 6.5 , reset. there are several methods by which the memory and register initialization can take place. each of these methods is referred to as a boot mode. the boot mode to be used is selected at reset. for more information on the bootmode selections, see section 3.4.1 , boot modes. the device is booted through multiple means?primary bootloaders within internal rom or emifa, and secondary user bootloaders from peripherals or external memories. boot modes, pin configurations, and register configurations required for booting the device, are described in the following subsections. the dm6433 boot modes are determined by these device boot and configuration pins. for information on how these pins are sampled at device reset, see section 6.5.1.2 , latching boot and configuration pins. bootmode[3:0] pcien fastboot aem[2:0] pllms[2:0] note: the pllms[2:0] configuration pins are actually multiplexed with the aeaw[2:0] configuration pins. for more details on the multiplexed aeaw[2:0]/pllms[2:0] configuration pins and control, see section 3.5.1.2 , emifa address width selects (aeaw[2:0]) and fastboot pll multiplier selects (pllms[2:0]). bootmode[3:0] and pcien determine the type of boot (e.g., i2c boot, emifa boot, hpi boot, or pci boot, etc.). fastboot determines if the pll is enabled during boot to speed up the boot process. the combination of aem[2:0] and pllms[2:0] is used by bootloader code to determine the pll multiplier used during fastboot modes (fastboot = 1). the dm6433 boot modes are grouped into three categories?non-fastboot modes, fixed-multiplier fastboot modes, and user-select multiplier fastboot modes. non-fastboot modes (fastboot = 0): the device operates in default pll bypass mode during boot. the non-fastboot bootmodes available on the dm6433 are shown in table 3-5 . fixed-multiplier fastboot modes (fastboot = 1, aem[2:0] = 001b): the bootloader code speeds up the device during boot according to the fixed pll multipliers. the fixed-multiplier fastboot bootmodes available on the dm6433 are shown in table 3-6 . note: the pllms[2:0] configurations have no effect on the fixed-multiplier fastboot modes, as these pins function as aeaw[2:0] to select the emifa address width when aem[2:0] = 001b. user-select multiplier fastboot modes (fastboot = 1, aem[2:0] = 000b,011b,100b,101b): the bootloader code speeds up the device during boot. the pll multiplier is selected by the user via the pllms[2:0] pins. the user-select multiplier fastboot bootmodes available on the dm6433 are shown in table 3-7 . all other modes not shown in these tables are reserved and invalid settings. submit documentation feedback device configurations 75
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-5. non-fastboot modes (fastboot = 0) device boot and pllc1 clock setting at boot configuration pins dm6433 dmp dspbootaddr boot description (1) device (master/slave) (default) (1) pll clkdiv1 domain bootmode[3:0] pcien frequency mode (2) (sysclk1 divider) (sysclk1) 0000 0 or 1 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 0001 0 or 1 reserved ? ? ? ? ? 0 hpi boot slave bypass /1 clkin 0x0010 0000 0010 1 reserved ? ? ? ? ? 0011 0 or 1 reserved ? ? ? ? ? emifa rom direct boot 0100 0 or 1 master bypass /1 clkin 0x4200 000 [pll bypass mode] i2c boot 0101 0 or 1 master bypass /1 clkin 0x0010 0000 [standard mode] (3) 16-bit spi boot 0110 0 or 1 master bypass /1 clkin 0x0010 0000 [mcbsp0] 0111 0 or 1 nand flash boot master bypass /1 clkin 0x0010 0000 uart boot without 1000 0 or 1 hardware flow control master bypass /1 clkin 0x0010 0000 [uart0] 1001 0 or 1 reserved ? ? ? ? ? 1010 0 or 1 vlynq boot slave bypass /1 clkin 0x0010 0000 1011 0 or 1 reserved ? ? ? ? ? 1100 0 or 1 reserved ? ? ? ? ? 1101 0 or 1 reserved ? ? ? ? ? uart boot with 1110 0 or 1 hardware flow control master bypass /1 clkin 0x0010 0000 [uart0] 24-bit spi boot 1111 0 or 1 master bypass /1 clkin 0x0010 0000 (mcbsp0 + gp[97]) (1) for all boot modes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) the pll mode for non-fastboot modes is fixed as shown in this table; therefore, the pllms[2:0] configuration pins have no effect on the pll mode. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. 76 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-6. fixed-multiplier fastboot modes (fastboot = 1, aem[2:0] = 001b) device boot and pllc1 clock setting at boot configuration pins dm6433 dmp dspbootaddr boot description (1) device (master/slave) (default) (1) pll clkdiv1 domain bootmode[3:0] pcien frequency mode (2) (sysclk1 divider) (sysclk1) 0000 0 or 1 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 hpi boot with pll 0 slave x27 /2 clkin x27 / 2 0x0010 0000 multiplier x27 at boot 0001 1 reserved ? ? ? ? ? hpi boot with pll 0 slave x20 /2 clkin x20 / 2 0x0010 0000 multiplier x20 at boot 0010 1 reserved ? ? ? ? ? hpi boot with pll 0 slave x15 /2 clkin x15 / 2 0x0010 0000 multiplier x15 at boot 0011 1 reserved ? ? ? ? ? emifa rom fastboot 0100 0 or 1 with application image master x20 /2 clkin x20 / 2 0x0010 000 script (ais) i2c boot 0101 0 or 1 master x20 /2 clkin x20 / 2 0x0010 0000 [fast mode] (3) 16-bit spi boot 0110 0 or 1 master x20 /2 clkin x20 / 2 0x0010 0000 [mcbsp0] 0111 0 or 1 nand flash boot master x20 /2 clkin x20 / 2 0x0010 0000 uart boot without 1000 0 or 1 hardware flow control master x20 /2 clkin x20 / 2 0x0010 0000 [uart0] emifa rom fastboot 1001 0 or 1 master x20 /2 clkin x20 / 2 0x0010 0000 without ais 1010 0 or 1 vlynq boot slave x20 /2 clkin x20 / 2 0x0010 0000 1011 0 or 1 reserved ? ? ? ? ? 1100 0 or 1 reserved ? ? ? ? ? 1101 0 or 1 reserved ? ? ? ? ? uart boot with 1110 0 or 1 hardware flow control master x20 /2 clkin x20 / 2 0x0010 0000 [uart0] 24-bit spi boot 1111 0 or 1 master x20 /2 clkin x20 / 2 0x0010 0000 (mcbsp0 + gp[97]) (1) for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) the pll mode for fixed-multiplier fastboot modes is fixed as shown in this table; therefore, the pllms[2:0] configuration pins have no effect on the pll mode. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. submit documentation feedback device configurations 77
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-7. user-select multiplier fastboot modes (fastboot = 1, aem[2:0] = 000b, 011b, 100b, or 101b) device boot and pllc1 clock setting at boot configuration pins dm6433 dmp dspbootaddr boot description (1) device (master/slave) (default) (1) pll clkdiv1 domain bootmode[3:0] pcien frequency mode (2) (sysclk1 divider) (sysclk1) 0000 0 or 1 no boot (emulation boot) master bypass /1 clkin 0x0010 0000 0 reserved ? ? ? ? ? 0001 pci boot without auto 1 slave table 3-8 /2 table 3-8 0x0010 0000 initialization 0 hpi boot slave table 3-8 /2 table 3-8 0x0010 0000 0010 pci boot with auto 1 slave table 3-8 /2 table 3-8 0x0010 0000 initialization 0011 0 or 1 reserved ? ? ? ? ? emifa rom fastboot 0100 0 or 1 master table 3-8 /2 table 3-8 0x0010 0000 with ais i2c boot 0101 0 or 1 master table 3-8 /2 table 3-8 0x0010 0000 [fast mode] (3) 16-bit spi boot 0110 0 or 1 master table 3-8 /2 table 3-8 0x0010 0000 [mcbsp0] 0111 0 or 1 nand flash boot master table 3-8 /2 table 3-8 0x0010 0000 uart boot without 1000 0 or 1 hardware flow control master table 3-8 /2 table 3-8 0x0010 0000 [uart0] emifa rom fastboot 1001 0 or 1 master table 3-8 /2 table 3-8 ? without ais 1010 0 or 1 vlynq boot slave x20 /2 clkin x20 / 2 0x0010 0000 1011 0 or 1 reserved ? ? ? ? ? 1100 0 or 1 reserved ? ? ? ? ? 1101 0 or 1 reserved ? ? ? ? ? uart boot with 1110 0 or 1 hardware flow control master table 3-8 /2 table 3-8 0x0010 0000 [uart0] 24-bit spi boot 1111 0 or 1 master x20 /2 clkin x20 / 2 0x0010 0000 (mcbsp0 + gp[97]) (1) for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). (2) any supported pll mode is available. [see table 3-8 for supported dm6433 pll mode options]. (3) i2c boot (bootmode[3:0] = 0101b) is only available if the mxi/clkin frequency is between 21 mhz to 30 mhz. i2c boot is not available for mxi/clkin frequencies less than 21 mhz. table 3-8. pll multiplier selection (pllms[2:0]) in user-select multiplier fastboot modes (fastboot = 1; aem[2:0] = 000b, 011b, 100b, or 101b) device boot and pllc1 clock setting at boot configuration pins clkdiv1 domain pllms[2:0] pll mode device frequency (sysclk1) (sysclk1 divider) 000 x20 /2 clkin x20 / 2 001 x15 /2 clkin x15 / 2 010 x16 /2 clkin x16 / 2 011 x18 /2 clkin x18 / 2 100 x22 /2 clkin x22 / 2 101 x25 /2 clkin x25 / 2 110 x27 /2 clkin x27 / 2 111 x30 /2 clkin x30 / 2 device configurations 78 submit documentation feedback
3.4.1.1 fastboot tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 as shown in table 3-5 , table 3-6 , and table 3-7 , at device reset the boot controller defaults the dspbootaddr to one of two values based on the boot mode selected. in all boot modes, the c64x+ is immediately released from reset and begins executing from address location indicated in dspbootaddr. internal bootloader rom (0x0010 0000): for most boot modes, the dspbootaddr defaults to the internal bootloader rom so that the dsp can immediately execute the bootloader code in the internal rom. the bootloader code decodes the captured bootmode, fastboot, pcien, default aem (daem), and pllms information (in the bootcfg register) to determine the proper boot operation. note: for all boot modes that default to dspbootaddr = 0x0010 0000, the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram. if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). emifa chip select space 2 (0x4200 0000): the emifa rom direct boot in pll bypass mode (bootcfg settings bootmode[3:0] = 0100b, fastboot = 0) is the only exception where the dspbootaddr defaults to the emifa chip select space 2. the dsp begins execution directly from the external rom at this emifa space. for more information how the bootloader code handles each boot mode, see using the tms320dm643x bootloader application report (literature number spraag0 ). when dm6433 exits pin reset ( reset or por released), the pll controllers (pllc1 and pllc2) default to pll bypass mode. this means the plls are disabled, and the mxi/clkin clock input is driving the chip. all the clock domain divider ratios discussed in section 6.3.4 , dm6433 power and clock domains, still apply. for example, assume an mxi/clkin frequency of 27 mhz?meaning the internal clock source for emifa is at clkdiv3 domain = 27 mhz/3 = 9 mhz, a very slow clock. in addition, the emifa registers are reset to the slowest configuration which translates to very slow peripheral operation/boot. to optimize boot time, the user should reprogram clock settings via the pllc as early as possible during the boot process. the fastboot pin facilitates this operation by allowing the device to boot at a faster clock rate. except for the emifa rom direct boot in pll bypass mode (bootcfg settings bootmode[3:0] = 0100b, fastboot = 0), all other boot modes default to executing from the internal bootloader rom. the first action that the bootloader code takes is to decode the boot mode. if the fastboot option is selected (bootcfg.fastboot = 1), the bootloader software begins by programming the pllc1 (system pllc) to pll mode to give the device a slightly faster operation before fetching code from external devices. the exact pll multiplier that the bootloader uses is determined by the aem[2:0] and pllms[2:0] settings, as shown in table 3-6 and table 3-7 . some boot modes must be accompanied with fastboot = 1 so that the corresponding peripheral can run at a reasonable rate to communicate to the external device(s). this includes pci boot. note: pllc2 still stays in pll bypass mode, the bootloader does not reconfigure it. submit documentation feedback device configurations 79
3.4.1.2 selecting fastboot pll multiplier 3.4.1.3 emifa boot modes tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-6 , table 3-7 , and table 3-8 show the pll multipliers used by the bootloader code during fastboot (fastboot = 1) and the resulting device frequency. the user is responsible for selecting the bootmode with the appropriate pll multiplier for their mxi/clkin clock source so that the device speed and pll frequency range requirements are met. for the pllc1 clock frequency ranges, see table 6-15 , pllc1 clock frequency ranges in section 6.7.1 , pll1 and pll2. the following are guidelines for pll output frequency and device speed (frequency): pll output frequency: (pllout = clkin frequency * boot pll multiplier) must stay within the pllout frequency range in table 6-15 , pllc1 clock frequency ranges. device frequency: (sysclk1) calculated from table 3-6 and table 3-7 must not exceed the sysclk1 maximum frequency in table 6-15 , pllc1 clock frequency ranges. for example, for a 600-mhz device with a clkin = 27 mhz, in order to stay within the pllout frequency range and sysclk1 maximum frequency from table 6-15 , pllc1 clock frequency ranges, the user must select a boot mode with a pll1 multiplier between x15 and x22. as shown in table 3-5 , table 3-6 , and table 3-7 , there are different types of emifa boot modes. this subsection summarizes these types of emifa boot modes. for further detailed information, see the using the tms320dm643x bootloader application report (literature number spraag0 ). emifa rom direct boot in pll bypass mode (fastboot = 0, bootmode[3:0] = 0100b) ? the c64x+ fetches the code directly from emifa chip select 2 space [ em_cs2] (address 0x4200 0000) ? the pll is in bypass mode ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1] or 011b [8-bit emifa (async) pinout mode 3]. if aem[2:0] = 001b, aeaw[2:0] must be configured to 100b. emifa rom fastboot with ais (fastboot = 1, bootmode[3:0] = 0100b) ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? the bootloader code programs pllc1 to pll mode to speed up the boot process. the pll multiplier value is determined by the aem[2:0] and pllms[2:0] configurations as shown in table 3-6 and table 3-7 . ? the bootloader code reads code from the emifa em_cs2 space using the application image script (ais) format. ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1] or 011b [8-bit emifa (async) pinout mode 3]. if aem[2:0] = 001b, aeaw[2:0] must be configured to 100b. emifa rom fastboot without ais: (fastboot = 1, bootmode[3:0] = 1001b) ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? the bootloader code programs pllc1 to pll mode to speed up the boot process. the pll multiplier value is determined by the aem[2:0] and pllms[2:0] configurations as shown in table 3-6 and table 3-7 . ? the bootloader code then jumps to the emifa em_cs2 space, at which point the c64x+ fetches the code directly from address 0x4200 0000. ? emifa is configured as asynchronous emif. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] must be configured to 001b [8-bit emifa (async) pinout mode 1] or 011b [8-bit emifa (async) pinout mode 3]. if aem[2:0] = 001b, aeaw[2:0] must be configured to 100b. nand flash boot: (fastboot = 0 or 1, bootmode[3:0] = 0111b) device configurations 80 submit documentation feedback
3.4.1.4 serial boot modes (i2c, uart[uart0], spi[mcbsp0]) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 ? the c64x+ begins execution from the internal bootloader rom at address 0x0010 0000. ? depending on the fastboot, aem[2:0], and pllms[2:0] settings, the bootloader code may program the pllc1 to pll mode to speed up the boot process. see table 3-5 , table 3-6 , and table 3-7 . ? the bootloader code reads the code from emifa (nand) em_cs2 (address 0x4200 0000) using ais format. ? emifa is configured in nand mode. the user is responsible for ensuring the desirable asynchronous emif pins are available through configuration pins aem[2:0] and aeaw[2:0]. aem[2:0] can be configured to 001b [8-bit emifa (async) pinout mode 1], 011b [8-bit emifa (async) pinout mode 3], 100b [8-bit emifa (nand) pinout mode 4], or 101b [8-bit emifa (nand) pinout mode 5]. if aem[2:0] = 001b, aeaw[2:0] must be configured to 100b. this subsection discusses how the bootloader configures the clock dividers for the serial boot modes?i2c boot, uart boot, and spi boot. 3.4.1.4.1 i2c boot if fastboot = 0, then i2c boot (bootmode = 0101) is performed in standard-mode (up-to 100 kbps). if fastboot = 1, then i2c boot is performed in fast-mode (up-to 400 kbps). the actual i2c data transfer rate is dependent on the mxi/clkin frequency. this is how the bootloader programs the i2c: i2c boot in fast-mode (bootmode[3:0] = 0101b, fastboot = 1) ? i2c register settings: icpsc.ipsc = 2 10 , icclkl.iccl = 8 10 , icckh.icch = 8 10 ? resulting in the following i2c prescaled module clock frequency (internal i2c clock): (clkin frequency in mhz) / 3 ? resulting in the following i2c serial clock (scl): scl frequency (in khz) = (clkin frequency in mhz) / 78 * 1000 scl low pulse duration (in m s) = 39 / (clkin frequency in mhz) scl high pulse duration (in m s) = 39 / (clkin frequency in mhz) i2c boot in standard-mode (bootmode[3:0] = 0101b, fastboot = 0) ? i2c register settings: icpsc.ipsc = 2 10 , icclkl.iccl = 45 10 , icckh.icch = 45 10 ? resulting in the following i2c prescaled module clock frequency (internal i2c clock): (clkin frequency in mhz) / 3 ? resulting in the following i2c serial clock (scl): scl frequency (in khz) = (clkin frequency in mhz) / 300 * 1000 scl low pulse duration (in m s) = 150 / (clkin frequency in mhz) scl high pulse duration (in m s) = 150 / (clkin frequency in mhz) note: the i2c peripheral requires that the prescaled module clock frequency must be between 7 mhz and 12 mhz. therefore, the i2c boot is only available for mxi/clkin frequency between 21 mhz and 30 mhz. for more details on the i2c periperhal configurations and clock requirements, see the tms320dm643x dmp inter-integrated circuit (i2c) peripheral user?s guide (literature number spru991 ). submit documentation feedback device configurations 81
3.4.1.5 host boot modes tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com 3.4.1.4.2 uart boot for uart boot (bootmode[3:0] = 1000b or 1110b), the bootloader programs the uart0 peripheral as follows: uart0 divisor is set to 15 10 resulting in this uart0 baud rate in kilobit per second (kbps): ? (clkin frequency in mhz) * 1000 / (15 * 16) the user is responsible for ensuring the resulting baud rate is appropriate for the system. the uart0 divisor (/15) is optimized for clkin frequency between 27 to 29 mhz to stay within 5% of the 115200-bps baud rate. for more details on the uart peripheral configurations and clock generation, see the tms320dm643x dmp universal asynchronous receiver/transmitter (uart) user's guide (literature number spru997 ). 3.4.1.4.3 spi boot both 16-bit address spi boot (bootmode = 0110) and 24-bit address spi boot are performed through the mcbsp0 peripheral. the bootloader programs the mcbsp0 peripheral as follows: mcbsp0 register settings: srgr.clkgdv = 2 10 resulting in this spi serial clock frequency: ? (sysclk3 frequency in mhz) / 3 sysclk3 frequency = sysclk1 frequency / 6. sysclk1 frequency during boot can be found in table 3-5 , table 3-6 , table 3-7 , and/or table 3-8 based on the boot mode selection. for example, if bootmode[3:0] = 0110b, fastboot = 1, the mxi/clkin frequency = 27 mhz, aem[2:0] = 000b, pllms[2:0] = 100b, the combination of table 3-7 and table 3-8 indicates that the device frequency (sysclk1) is clkin x 22 / 2 = 297 mhz. this means sysclk3 frequency is 297 / 6 = 49.5 mhz, resulting in spi serial clock frequency of 49.5 / 3 = 16.5 mhz. the dm6433 supports two types of host boots?pci boot or hpi boot. the pci boot (bootmode[3:0] = 0001b or 0010b, pcien = 1) is only available in fastboot (fastboot = 1), as shown in table 3-6 and table 3-7 . the hpi boot is available in fastboot and non-fastboot, as shown in table 3-5 , table 3-6 , and table 3-7 . note: the hpi hstrobe inactive pulse duration timing requirement [t w(hstbh) ] is dependent on the hpi internal clock source (sysclk3) frequency (see section 6.13.3 , hpi electrical data/timing). the external host must be aware of the sysclk3 frequency during boot to ensure the hstrobe pulse duration timing requirement is met. 82 device configurations submit documentation feedback
3.4.2 bootmode registers 3.4.2.1 bootcfg register tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the device bootmode (see section 3.4.1 , boot modes) and configuration pins (see section 3.5.1 , device and peripheral configurations at device reset) latched at reset are captured in the device boot configuration (bootcfg) register which is accessible through the system module. this is a read-only register. the bits show the values latched from the corresponding configuration pins sampled at device reset. for more information on how these pins are sampled at device reset, see section 6.5.1.2 , latching boot and configuration pins. for the corresponding device boot and configuration pins, see table 2-5 , boot terminal functions. 31 20 19 18 17 16 reserved fastboot rsv dpcien rsv r-0000 0000 0001 r-l r-0 r-l r-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsv pllms rsv daem reserved bootmode r-0 r-lll r-0 r-lll r-0000 r-llll legend: r = read only; l = pin state latched at reset rising edge; - n = value after reset figure 3-3. bootcfg register?0x01c4 0014 submit documentation feedback device configurations 83
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-9. bootcfg register description bit field name description 31:20 reserved reserved. writes have no effect. fastboot (see section 3.4.1.1 , fastboot) this field is used by the device bootloader code to determine if it needs to speed up the device to pll mode before booting. 19 fastboot 0 = no fastboot 1 = fastboot the default value is latched from fastboot configuration pin. 18 rsv reserved. writes have no effect. pinmux1.pcien default (see section 3.5.1.3 , pci enable) for more details on the pcien settings, see section 3.7.2.2 , pinmux1 register description. this field affects the pin mux control by setting the default of pinmux1.pcien. this field determines if the internal pullup/pulldown resistors on the pci capable pins are enabled/disabled. this field does not affect pci 17 dpcien register setting. the user must keep the value on the pcien pin constant throughout the operation. the default value is from the pcien configuration pin. 16:15 rsv reserved. writes have no effect. pinmux0.aeaw default [aeaw] and fastboot pll multiplier select [pllms] (see section 3.5.1.2 , emifa address width select [aeaw] and fast boot pll multiplier select [pllms]) the aeaw[2:0]/pllms configuration pins serve two purposes: aeaw[2:0]: 8-bit emifa (async) pinout mode 1 address width if aem = 001, this field serves as aeaw and it indicates the 8-bit emifa (async) pinout mode 1 address width. in this case, this field affects pin mux control only by setting the default of pin mux control register 14:12 pllms pinmux0.aeaw[2:0]. this field does not affect emifa register settings. for more details on the aeaw settings, see section 3.7.2.1 , pinmux0 register description. pllms: fastboot pll multiplier select if fastboot = 1 and aem[2:0] = 000b, 011b, 100b, or 101b, this field selects the fastboot pll multiplier. in this case, this field does not affect the pin mux control or the emifa register settings. the bootloader code uses this field to determine the pll multiplier used for fastboot. 11 rsv reserved. writes have no effect. pinmux0.aem default [daem] (see section 3.5.1.1 , emifa pinout mode (aem[2:0])) for more details on the aem settings, see section 3.7.2.1 , pinmux0 register description. 10:8 daem this field affects pin mux control by setting the default of pinmux0.aem. this field does not affect emifa register settings. the default value is latched from the aem[2:0] configuration pins. 7:4 reserved reserved. writes have no effect. boot mode (see section 3.4.1 , boot modes) this field is used in conjunction with fastboot, pcien, aem, and pllms to determine the device boot 3:0 bootmode mode. the default value is latched from the bootmode[3:0] configuration pins. device configurations 84 submit documentation feedback
3.4.2.2 bootcmplt register tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 if the bootloader code detects an error during boot, it records the error status in the boot complete (bootcmplt) register. in addition, the bootcmplt register is used for communication between the external host and the bootloader code during a host boot (hpi boot or pci boot). once the external host has completed boot, it must perform the following communication with the bootloader code: write the desired 32-bit cpu starting address in the dspbootaddr register (see section 3.4.2.3 , dspbootaddr register). write a ?1? to the boot complete (bc) bit field in the bootcmplt register to indicate that the host has completed booting this device. once the bootloader code detects bc = 1, it directs the cpu to begin executing from the dspbootaddr register. the bootcmplt register is reset by any device-level global reset. for the list of device-level global resets, see section 6.5 , reset. 31 20 19 16 reserved err r/w-0000 0000 0000 r/w-0000 15 1 0 reserved bc r/w- 0000 0000 0000 000 r/w-0 legend: r = read; w = write; - n = value after reset figure 3-4. bootcmplt register? 0x01c4 000c table 3-10. bootcmplt register description bit field name description 31:20 reserved reserved. for proper device operation, the user should only write "0" to these bits. boot error 0000 = no error (default). 19:16 err 0001 - 1111 = bootloader software detected a boot error and aborted the boot. for the error codes, see the using the tms320dm643x dmp bootloader application report (literature number spraag0 ). 15:1 reserved reserved. for proper device operation, the user should only write "0" to these bits. boot complete flag from host this field is only applicable to host boots. 0 bc 0 = host has not completed booting this device (default). 1 = host has completed booting this device. dsp can begin executing from the dspbootaddr register value. submit documentation feedback device configurations 85
3.4.2.3 dspbootaddr register tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dsp boot address (dspbootaddr) register contains the starting address for the c64x+ cpu. whenever the c64x+ is released from reset, it begins executing from the location pointed to by dspbootaddr register. for host boots (hpi boot or pci boot), the dspbootaddr register is also used for communication between the host and the bootloader code during boot. the dspbootaddr register is reset by any device-level global reset. for the list of device-level global resets, see section 6.5 , reset. 31 0 dspbootaddr r/w-0x0010 0000 or 0x4200 00000 legend: r = read; w = write; - n = value after reset figure 3-5. dspbootaddr register? 0x01c4 0008 table 3-11. dspbootaddr register description bit field name description dsp boot address after boot, the c64x+ cpu begins execution from this 32-bit address location. the lower 10 bits (bits 9:0) should always be programmed to "0" as they are ignored by the c64x+. the default value of the dspbootaddr depends on the boot mode selected. 31:0 dspbootaddr the dspbootaddr defaults to 0x0010 0000 when the internal bootloader rom is used. or the dspbootaddr defaults to 0x4200 0000 when emifa cs2 space is used. for the boot mode selections, see table 3-5 , non-fastboot modes; table 3-6 , fixed-multiplier fastboot modes; and table 3-7 , user-select multiplier fastboot modes. for non-host boot modes, software can leave the dspbootaddr register at default. for host boots (hpi boot or pci boot), the dspbootaddr register is also used for communication between the host and the bootloader code during boot. for host boots, the dspbootaddr register defaults to internal bootloader rom, and the c64x+ cpu is immediately released from reset so that it can begin executing the bootloader code in this internal rom. the bootloader code waits for the host to boot the device. once the host is done booting the device, it must write a new starting address into the dspbootaddr register, and follow with writing bootcmplt.bc = 1 to indicate the boot is complete. as soon as the bootloader code detects bootcmplt.bc = 1, it instructs the cpu to jump to this new dspbootaddr address. at this point, the cpu continues the rest of the code execution starting from the new dspbootaddr location and the boot is completed. 86 device configurations submit documentation feedback
3.5 configurations at reset 3.5.1 device and peripheral configurations at device reset tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 some device configurations are determined at reset. the following subsections give more details. table 2-5 , boot terminal functions, lists the device boot and configuration pins that are latched at device reset for configuring basic device settings for proper device operation. table 3-12 , summarizes the device boot and configuration pins, and the device functions that they affect. table 3-12. default functions affected by device boot and configuration pins device boot and boot selected pin mux control global setting peripheral setting configuration pins bootmode[3:0] boot mode pinmux0/pinmux1 i/o pin power: psc/peripherals: registers: based on based on based on bootmode[3:0], the bootmode[3:0], the bootmode[3:0], the bootloader code programs bootloader code programs bootloader code programs vdd3p3v_pwdn register the psc to put pinmux0 and pinmux1 to power up the i/o pins boot-related peripheral(s) registers to select the required for boot. in the enable state, and appropriate pin functions programs the peripheral(s) required for boot. for boot operation. fastboot fastboot ? sets device frequency: ? based on bootmode, fastboot, pllms, and aem the bootloader code programs pllc1. aeaw[2:0]/pllms[2:0] if fastboot = 1 and pinmux0.aeaw: sets device frequency: ? aem = 000b, 011b, 100b if pinmux0.aem = 001b, based on bootmode, or 101b the pllms[2:0] aeaw[2:0] must be set to fastboot, pllms, and selects the fastboot 100b to configure aem the bootloader code pll multiplier. maximum address bus programs pllc1. width for emifa. affects the pin muxing in emifa/vpss sub-block 0. aem[2:0] together with fastboot pinmux0.aem: sets device frequency: psc/emifa: and pllms[2:0] , sets the default of this based on bootmode, the emifa module state determines the field to control the emifa fastboot, pllms, and defaults to swrstdisable fastboot pll pinout mode. aem the bootloader code if aem = 0; otherwise, the multiplier. programs pllc1. emifa module state affects the pin muxing in defaults to enable. emifa/vpss sub-block 0, 1, and 3. pcien (1) host boot: pinmux1.pcien: ? psc/peripheral pcien selects the type of sets this field to control (applicable to host boot host boot the pci pin muxing in only): (hpi boot or pci boot) host block, pci data based on the host boot block, gpio block, type (pci or hpi), the emifa/vpss sub-block 0 bootloader code programs and sub-block 3. the psc to put the (1) (2) corresponding peripheral in the enable state, and programs the peripheral for boot operation. (1) software can modify all pinmux0 and pinmux1 bit fields from their defaults, except for pinmux1.pcien. (2) in addition to pin mux control, pcien also affects the internal pullup/down resistors of the pci capable pins. when pcien = 0, internal pullup/down resistors on the pci capable pins are enabled. when pcien = 1, internal pullup/down resistors on the pci capable pins are disabled to be compliant to the pci local bus specification revision 2.3. submit documentation feedback device configurations 87
3.5.1.1 emifa pinout mode (aem[2:0]) 3.5.1.2 emifa address width select (aeaw) and fastboot pll multiplier select (pllms) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com for proper device operation, external pullup/pulldown resistors may be required on these device boot and configuration pins. for discussion situations where external pullup/pulldown resistors are required, see section 3.9.1 , pullup/pulldown resistors. note: except for pcien, all other dm6433 configuration inputs (bootmode[3:0], fastboot, aeaw[2:0]/pllms[2:0] and aem[2:0]) are multiplexed with other functional pins. these pins function as device boot and configuration pins only during device reset. the user must take care of any potential data contention in the system. to help avoid system data contention, the dm6433 puts these configuration pins into a high-impedance state (hi-z) when device reset ( reset or por) is asserted, and continues to hold them in a high-impedance state until the internal global reset is removed; at which point, the default peripheral (either gpio or emifa based on default of aem[2:0]) will now control these pins. all of the device boot and configuration pin settings are captured in the corresponding bit fields in the bootcfg register (see section 3.4.2.1 ). the following subsections provide more details on the device configurations determined at device reset: aem, aeaw/pllms, and pcien. to support different usage scenarios, the dm6433 provides intricate pin multiplexing between the emifa and other peripherals. the pinmux0.aem register bit field in the system module determines the emifa pinout mode. the aem[2:0] pins only select the default emifa pinout mode. it is latched at device reset de-assertion (high) into the bootcfg.daem bit field. the aem[2:0] value also sets the default of the pinmux0.aem bit field. while the bootcfg.daem bit field shows the actual latched value and cannot be modified, the pinmux0.aem value can be changed by software to modify the emifa pinout mode. note: the aem[2:0] value does not affect the operation of the emifa module itself. it only affects which emifa pins are brought out to the device pins. for more details on the aem settings, see section 3.7 , multiplexed pin configurations. in addition, for fastboot modes (fastboot = 1), the bootloader code determines the pll1 multiplier based on the default settings of aem[2:0] and pllms[2:0]. for more details, see section 3.4.1.1 , fastboot, and section 3.5.1.2 , emifa address width select (aeaw) and fastboot pll multiplier select (pllms). the aeaw[2:0]/pllms[2:0] pins serve two functional purposes (aeaw or pllms), depending on the fastboot and aem settings. the aeaw[2:0]/pllms[2:0] pins are latched at device reset de-assertion (high) and captured in the bootcfg.pllms bit field. this value also sets the default of the pinmux0.aeaw field. while the bootcfg.pllms field shows the actual latched value and cannot be modified, the pinmux0.aeaw value can be changed by software to modify the emifa pinout. aeaw as emifa address width select (aeaw) if aem[2:0] = 001b [8-bit emifa (async) pinout mode 1], the aeaw[2:0]/pllms[2:0] pins serve as aeaw to set the default of the emifa address width selection. on dm6433, only aeaw = 100b is supported. if aem[2:0] = 001b [8-bit emifa (async) pinout mode 1], aeaw must be set to 100b to select full addres width for emifa. for other emifa pinout modes (aem not 001b), aeaw is not applicable in determining the emifa address width. note: aeaw[2:0] value does not affect the operation of the emifa module itself. 88 device configurations submit documentation feedback
3.5.1.3 pci enable (pcien) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 aeaw as fast boot pll multiplier select (pllms) if fastboot = 1 and aem[2:0] = 000b [no emifa], 011b [8-bit emifa (async) pinout mode 3], 100b [8-bit emifa (nand) pinout mode 4], or 101b [8-bit emifa (nand) pinout mode 5], the aeaw[2:0]/pllms[2:0] pins serve as pllms to select pll multiplier for fastboot modes. for more information on boot modes and the fastboot pll multiplier selection, see section 3.4.1 , boot modes. the pcien configuration pin determines if the pci peripheral is used on this device. if pcien = 1 indicating the pci is used, then the pci multiplexed pins default to pci functions, and the pins? corresponding internal pullup/pulldown resistors are disabled. if pcien = 0 indicating the pci is not used, then the pci muxed pins default to non-pci functions, and the pins? corresponding internal pullup/pulldown resistors are enabled. the pcien setting is captured and stored in the bootcfg.dpcien bit field, and also in the pinmux1.pcien bit field. these values cannot be changed by software. furthermore, for proper device operation, the user must hold the desired setting at the pcien pin throughout device operation. submit documentation feedback device configurations 89
3.6 configurations after reset 3.6.1 switch central resource (scr) bus priorities tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the following sections provide details on configuring the device after reset. multiplexed pins are configured both at and after reset. section 3.5.1 , device and peripheral configurations at device reset, discusses multiplexed pin control at reset. for more details on multiplexed pins control after reset, see section 3.7 , multiplexed pin configurations. prioritization within the switched central resource (scr) is programmable for each master. the register bit fields and default priority levels for dm6433 bus masters are shown in table 3-13 , dm6433 default bus master priorities. the priority levels should be tuned to obtain the best system performance for a particular application. lower values indicate higher priority. for most masters, their priority values are programmed at the system level by configuring the mstpri0 and mstpri1 registers. details on the mstpri0/1 registers are shown in figure 3-6 and figure 3-7 . the c64x+, vpss, and edma masters contain registers that control their own priority values. table 3-13. dm6433 default bus master priorities priority bit field bus master default priority level vpssp vpss 0 (vpss pcr register) edmatc0p edmatc0 0 (edmacc quepri register) edmatc1p edmatc1 0 (edmacc quepri register) edmatc2p edmatc2 0 (edmacc quepri register) c64x+_dmap c64x+ (dma) 7 (c64x + mdmaarbe.pri field) c64x+_cfgp c64x+ (cfg) 1 (mstpri0 register) emacp emac 4 (mstpri1 register) vlynqp vlynq 4 (mstpri1 register) hpip hpi 4 (mstpri1 register) pcip pci 4 (mstpri1 register) 31 16 reserved r-0000 0000 0000 0000 15 11 10 8 7 0 reserved c64x+_cfgp reserved r-0000 0 r/w-001 r-0000 0000 legend: r = read; w = write; - n = value after reset figure 3-6. mstpri0 register? 0x01c4 003c table 3-14. mstpri0 register description bit field name description 31:11 reserved reserved. read-only, writes have no effect. c64x+_cfg master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 10:8 c64x+_cfgp 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) device configurations 90 submit documentation feedback
3.6.2 peripheral selection after device reset tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-14. mstpri0 register description (continued) bit field name description 7:0 reserved reserved. read-only, writes have no effect. 31 27 26 25 24 23 22 21 20 19 18 17 16 reserved pcip rsv hpip rsv vlynqp r-0000 0 r/w-100 r-0 r/w-100 r-0 r/w-100 15 3 2 1 0 reserved emacp r- 0000 0000 0000 0 r/w-100 legend: r = read; w = write; - n = value after reset figure 3-7. mstpri1 register? 0x01c4 0040 table 3-15. mstpri1 register description bit field name description 31:27 reserved reserved. read-only, writes have no effect. pci master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 26:24 pcip 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 23 rsv reserved. read-only, writes have no effect. hpi master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 22:20 hpip 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 19 rsv reserved. read-only, writes have no effect. vlynq master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 18:16 vlynqp 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) 15:3 reserved reserved. read-only, writes have no effect. emac master port priority in system infrastructure. 000 = priority 0 ( highest) 100 = priority 4 2:0 emacp 001 = priority 1 101 = priority 5 010 = priority 2 110 = priority 6 011 = priority 3 111 = priority 7 ( lowest) after device reset, most peripheral configurations are done within the peripheral?s registers. this section discusses some additional peripheral controls in the system module. for information on multiplexed pin controls that determine what peripheral pins are brought out to the pins, see section 3.7 , multiplexed pin configurations. submit documentation feedback device configurations 91
3.6.2.1 hpi control register (hpictl) 3.6.2.2 timer control register (timerctl) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the hpi control (hpictl) register determines the host burst write time-out value. the user should only modify this register once during device initialization. when modifying this register, the user must ensure the hpi fifos are empty and there are no on-going hpi transactions. 31 16 reserved r-0000 0000 0000 0000 15 10 9 8 7 0 reserved reserved timout r- 0000 00 r/w-00 r/w-1000 0000 legend: r = read; w = write; - n = value after reset figure 3-8. hpictl register? 0x01c4 0030 table 3-16. hpictl register description bit field name description 31:10 reserved reserved. read-only, writes have no effect. 9:8 reserved reserved. for proper device operation, the user should only write "0" to these bits (default). host burst write timeout value when the hpi time-out counter reaches the value programmed here, the hpi write fifo content is flushed. for 7:0 timout more details on the time-out counter and its use in write bursting, see the tms320dm643x dmp host port interface (hpi) user's guide (literature number spru998 ). the timer control register (timerctl) provides additional control for timer0 and timer2. the user should only modify this register once during device initialization, when the corresponding timer is not in use. timer 2 control: the timerctl.wdrst bit determines if the watchdog timer event (timer 2) can cause a device max reset. for more details on the description of a maximum reset, see section 6.5.3 , maximum reset. timer 0 control: the tinp0sel bit selects the clock source connected to timer0's tin0 input. 31 16 reserved r-0000 0000 0000 0000 15 2 1 0 tinp0 wd reserved sel rst r- 0000 0000 0000 00 r/w-0 r/w-1 legend: r = read; w = write; - n = value after reset figure 3-9. timerctl register? 0x01c4 0084 device configurations 92 submit documentation feedback
3.6.2.3 edma tc configuration register (edmatccfg) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-17. timerctl register description bit field name description 31:2 reserved reserved. read-only, writes have no effect. timer0 external input (tin0) select 0 = timer0 external input comes directly from the tinp0l pin ( default). 1 tinp0sel 1 = timer0 external input is tinp0l pin divided by 6. for example, if tinp0l = 27mhz, timer0 input tin0 is 27mhz / 6 = 4.5 mhz. watchdog reset enable 0 wdrst 0 = watchdog timer event (wdint from timer2) does not cause device reset. 1 = watchdog timer event (wdint from timer2) causes a device max reset ( default). the edma transfer controller configuration (edmatccfg) register configures the default burst size (dbs) for edma tc0, edma tc1, and edma tc2. for more information on the correct usage of dbs, see the tms320dm643x dmp enhanced direct memory access (edma) controller user's guide (literature number spru987 ). the user should only modify this register once during device initialization and when the corresponding edma tc is not in use. 31 16 reserved r-0000 0000 0000 0000 15 6 5 4 3 2 1 0 reserved tc2dbs tc1dbs tc0dbs r-0000 0000 00 r/w-10 r/w-01 r/w-00 legend: r = read; w = write; - n = value after reset figure 3-10. edmatccfg register? 0x01c4 0088 table 3-18. edmatccfg register description bit field description 31:6 reserved reserved. read-only, writes have no effect. edma tc2 default burst size 00 = 16 byte 01 = 32 byte 10 = 64 byte ( default) 5:4 tc2dbs 11= reserved edma tc2 is intended for pci or miscellaneous transfers. tc2 fifo size is 128 bytes, regardless of default burst size setting. edma tc1 default burst size 00 = 16 byte 01 = 32 byte ( default) 10 = 64 byte 3:2 tc1dbs 11 = reserved edma tc1 is intended for high throughput bulk transfers. tc1 fifo size is 256 bytes, regardless of default burst size setting. edma tc0 default burst size 00 = 16 byte ( default) 01 = 32 byte 10 = 64 byte 1:0 tc0dbs 11 = reserved edma tc0 is intended for short burst transfers with stringent deadlines (e.g., mcbsp, mcasp). tc0 fifo size is 128 bytes, regardless of default burst size setting. submit documentation feedback device configurations 93
3.7 multiplexed pin configurations tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com dm6433 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions in the smallest possible package, providing ultimate flexibility for end applications. the pin multiplex registers pinmux0 and pinmux1 in the system module are responsible for controlling all pin multiplexing functions on the dm6433. the default setting of some of the pinmux0 and pinmux1 bit fields are configured by configuration pins latched at reset (see section 3.5.1 , device and peripheral configurations at device reset). after reset, software may program the pinmux0 and pinmux1 registers to switch pin functionalities. the following peripherals have multiplexed pins: vpss (vpbe), emifa, pci, hpi, vlynq, emac, mcasp0, mcbsp0, pwm0, pwm1, pwm2, timer0, timer1, uart0, and gpio. the device is divided into the following pin multiplexed blocks (pin mux blocks): emifa/vpss block: vpss (vpbe), emifa, part of pci, gpio. this block is further subdivided into these sub-blocks: ? sub-block 0: part of emifa (data, address, control), part of pci, and gpio ? sub-block 1: vpbe (venc), part of emifa (data, address, control), and gpio ? sub-block 2: part of emifa (control signals em_wait/(rdy/ bsy), em_oe, and em_we) ? sub-block 3: part of emifa (address em_a[12:5]), part of pci, and gpio host block: hpi, vlynq, emac, part of pci, and gpio pci data block: part of pci gpio block: part of pci and gpio serial port block: mcbsp0, mcasp0, and gpio. this block is further sub-divided into sub-blocks. ? serial port sub-block 0: mcbsp0, part of mcasp0, and gpio ? serial port sub-block 1: part of mcasp0, and gpio uart0 flow control block: uart0 flow control, pwm0, and gpio uart0 data block: uart0 data and gpio timer0 block: timer0 and mcbsp0 clks pins timer1 block: timer1 pwm1 block: pwm1 and gpio clkout block: clkout0, pwm2, and gpio as shown in the list above, the pci, mcbsp0, and uart0 peripherals span multiple pin mux blocks. to use these peripherals, they must be selected in all relevant pin mux blocks. for more details, see section 3.7.3 , pin multiplexing details, and section 3.7.3.2 , peripherals spanning multiple pin mux blocks. note: there is no actual pin multiplexing in emifa/vpss sub-block 2 and the pci data block. however these are still considered "pin mux blocks" because they contain part of the pins necessary for emifa and pci, respectively. a high level view of the pin mux blocks is shown in figure 3-11 . in each pin mux block, the pinmux0/pinmux1 default settings are underlined. note: some default pin functions are determined by configuration pins (pcien, aeaw[2:0], aem[2:0]); therefore, more than one configuration setting can serve as default based on the configuration pin settings latched at device reset. 94 device configurations submit documentation feedback
3.7.1 pin muxing selection at reset tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 a. default settings for pinmux0 and pinmux1 registers are underlined. b. emifa/vpss block: shows the major config options based on the aem and pcien settings. actual pin functions in the emifa/vpss block are further determined by other pinmux fields. c. pci pins span multiple blocks (host block, gpio block, emifa/vpss block, and pci data block). for pci to be operational, pci pins must be selected in all of these pin mux blocks. for the emifa/vpss block, pci is only supported if aem = 000b or 101b. d. mcbsp0 pins span multiple blocks (serial port sub-block0 and timer0 block). serial port sub-block0 contains most of the pins needed for mcbsp0 operation. timer0 block contains the optional external clock source input clks0. figure 3-11. pin mux block selection this section summarizes pin mux selection at reset. submit documentation feedback device configurations 95 host block (27 pins) (a)(c) pci (27) pcien=1 hostbk=000 gpio (27) pcien=0 hostbk=000 vlynq (10) gpio (17) vlynq (10) emac (15) mdio (2) pcien=0 hostbk=001 pcien=0 hostbk=010 pcien=0 hostbk=011 pcien=0 hostbk=100 hpi (26) gpio (1) emac (15) mdio (2) gpio (10) gpio block (4 pins) (c) pci (4) pcien=1 gpio (4) pcien=0 uart0 data block (2 pins) gpio (2) ur0dbk=0 uart data (2) ur0dbk=1 uart0 flow control block (2 pins) gpio (2) ur0fcbk=00 uart0 flowctrl (2) ur0fcbk=01 pwm0 (1) ur0fcbk=10 gpio (1) timer1 block (2 pins) gpio (2) tim1bk=00 timer1 (2) tim1bk=01 timer0 block (2 pins) (d) gpio (2) tim0bk=00 timer0 (2) tim0bk=01 mcbsp0 clks0 (1) tim0bk=11 timer0 tinpol (1) pwm 1 block (1 pin) gpio (1) pwm1bk=0 pwm1 (1) pwm1bk=1 clkout block (1 pin) gpio (1) ckobk=00 clkout (1) ckobk=01 pwm2 (1) ckobk=10 serial port sub-block 0 (6 pins) (d) gpio (6) spbk0=00 mcbsp0 (6) spbk0=01 mcasp0 receive and 3 serializers (6) spbk0=10 serial port sub-block 1 (6 pins) gpio (6) spbk1=00 mcasp0 transmit and 1 serializer (6) spbk1=10 emifa/vpss block (61 pins) (a)(b)(c) 8-24b vpbe major config option a gpio 8-24b vpbe major configoption f gpio pci 8b vpbe major configoption b gpio 8b emifa (async) pinout mode 1 16mb per ce 8-16b vpbe major configoption c gpio 8b emifa (async) pinout mode 3 32kb per ce 8-16b vpbe major configoption d gpio 8b emifa (nand) pinout mode 4 8b vpbe major configoption e gpio 8b emifa (nand) pinout mode 5 8b vpbe major configoption g gpio 8b emifa (nand) pinout mode 5 pci pci data block (3 pins) (c) pci (3) not muxed aem=000,pcien=0 aem=001,pcien=0 aem=011, pcien=0 aem=100,pcien=0 aem=101,pcien=0 aem=000,pcien=1 aem=101,pcien=1 note: for major config option b, aeaw = 100. for all others, aeaw = dont care.
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the configuration pins aem[2:0], aeaw[2:0], and pcien latched at device reset determine default pin muxing for the following pin mux blocks: emifa/vpss block: default pin mux determined by aem[2:0], aeaw[2:0], and pcien. after reset, software may modify settings in the pinmux0 register to add vpbe functionalities into this block. however, after reset, software is not allowed to modify pinmux1.pcien setting to change pci pinout. ? aem[2:0] = 000b, aeaw[2:0] = don't care, pcien = 0: major config option a is selected. this block defaults to 61 gpio pins. ? aem[2:0] = 001b, aeaw[2:0] = 100b, pcien = 0: major config option b is selected. this block defaults to 8-bit emifa (async) pinout mode 1, plus 24 gpio pins. ? aem[2:0] = 011b, aeaw[2:0] = don't care, pcien = 0: major config option c is selected. this block defaults to 8-bit emifa (async) pinout mode 3, plus 33 gpio pins. ? aem[2:0] = 100b, aeaw[2:0] = don't care, pcien = 0: major config option d is selected. this block defaults to 8-bit emifa (nand) pinout mode 4, plus 47 gpio pins. ? aem[2:0] = 101b, aeaw[2:0] = don't care, pcien = 0: major config option e is selected. this block defaults to 8-bit emifa (nand) pinout mode 5, plus 47 gpio pins. ? aem[2:0] = 000b, aeaw[2:0] = don't care, pcien = 1: major config option f is selected. this block defaults to pci pins, plus 45 gpio pins. ? aem[2:0] = 101b, aeaw[2:0] = don't care, pcien = 1: major config option g is selected. this block defaults to 8-bit emifa (nand) pinout mode 5, pci pins, plus 31 gpio pins. host block: default pin mux determined by pcien. ? pcien = 0: the 27 pins in host block default to gpio function. software may program pinmux1.hostbk to modify pin functions after reset. ? pcien = 1: the 27 pins in host block serve as pci pins. software is not allowed to modify this setting after reset. gpio block: pin function determined by pcien configuration pin. ? pcien = 0: the 4 pins in gpio block serve as gpio pins. software is not allowed to modify this setting after reset. ? pcien = 1: the 4 pins in gpio block serve as pci pins. software is not allowed to modify this setting after reset. pci data block: pin function determined by pcien. ? pcien = 0: the 3 pins in pci data block have no function and should be left unconnected. software is not allowed to modify this setting after reset. ? pcien = 1: the 3 pins in pci data block serve as pci pins. software is not allowed to modify this setting after reset. for a description of the pinmux0 and pinmux1 registers and more details on pin muxing, see section 3.7.2 . 96 device configurations submit documentation feedback
3.7.2 pin muxing selection after reset 3.7.2.1 pinmux0 register description tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the pinmux0 and pinmux1 registers in the system module allow software to select the pin functions in the pin mux blocks. the pin control of some of the pin mux blocks requires a combination of pinmux0/pinmux1 bit fields. for more details on the combination of the pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6433. this section only provides an overview of the pinmux0 and pinmux1 registers. for more detailed discussion on how to program each pin mux block, see section 3.7.3 , pin multiplexing details. the pin multiplexing 0 register (pinmux0) controls the pin function in the emifa/vpss block. the pinmux0 register format is shown in figure 3-12 and the bit field descriptions are given in table 3-19 . some muxed pins are controlled by more than one pinmux bit field. for the combination of the pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6433. for more information on emifa/vpss block pin muxing, see section 3.7.3.13 , emifa/vpss block muxing. for the pin-by-pin muxing control of the emifa/vpss block, see section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary. note: in addition to pinmux0 bit fields, the emifa/vpss block also requires the pcien bit in the pin multiplexing 1 register (pinmux1, section 3.7.2.2 ) to determine the pci settings. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved aeaw r/w-0000 0000 0000 0 r/w-lll 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vpbe rgbsel cs3sel cs4sel cs5sel vencsel rsv aem cken r/w-0 r/w-000 r/w-00 r/w-00 r/w-00 r/w-00 r/w-0 r/w-lll legend: r/w = read/write; r = read only; l = pin state latched at reset rising edge; - n = value after reset (1) for proper dm6433 device operation, always write a value of "0" to all reserved/rsv bits. figure 3-12. pinmux0 register? 0x01c4 0000 (1) submit documentation feedback device configurations 97
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-19. pinmux0 register bit descriptions bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to these bits 31:19 rsv ( default). 8-bit emifa (async) pinout mode 1 address width select or fast boot pll multiplier select this field serves two purposes: sub-block 0 1. if aem = 001b, this field serves as the 8-bit emifa (async) pinout mode 1 em_a[13]/ad25/em_d[0]/gp[51] address width select. em_a[14]/ad27/em_d[1]/gp[50] 2. if fastboot = 1 and aem = 0 (000b), 3 (011b), 4 (100b), or 5 (101b), this em_a[15]/ad29/em_d[2]/gp[49] field serves as the fastboot pll multiplier select. em_a[16]/ pgnt/em_d[3]/gp[48] em_a[17]/ad31/em_d[4]/gp[47] fastboot pll multiplier select: for more details on the aeaw pin functions as 18:16 aeaw (1) em_a[18]/ prst/em_d[5]/gp[46] fastboot pll multiplier select, see section 3.4.1 , bootmodes. em_a[19]/ preq/em_d[6]/gp[45] emifa address width select: em_a[20]/ pinta/em_d[7]/gp[44] 000b through 011b = reserved. the combination of pinmux0/1 fields pcien, aem, and aeaw controls the muxing of these 8 100b = emifa (async) pinout supports address pins em_a[20:0]. pins. (2) emifa (async) signals em_a[20:13] are pinned out. 101b through 111b = reserved. vpbe clock select. sub-block 1 0 = gpio ( default) vpbeclk/gp[30] 15 vpbecken pin functions as gpio (gp[30]). the pinmux0 field vpbecken alone controls 1 = vpbe clock (vpbeclk) the muxing of this pin. pin functions as vpbe clock (vpbeclk). venc rgb mode and lcd_field select. 000b = no venc rgb mode or lcd_field supported. these pins function as gpio and/or emifa based on aem setting ( default). 001b = lcd_field mode. sub-block 1 venc lcd_field pin function is supported. the remaining 7 pins function as g0/ em_cs2/gp[12] gpio and/or emifa based on aem setting. b0/lcd_field/em_a[3]/gp[11] applicable only if aem = 0 (000b), 4 (100b), or 5 (101b). r0/em_a[4]/gp[10]/(aeaw2/pllms2) 010b = rgb666 mode. g1/em_a[1]/(ale)/gp[9]/aeaw1/pllms1) venc rgb666 pins (r2, b2) are supported, along with 6 gpio pins (gp[12:7]). b1/em_a[2]/(cle)/gp[8]/(aeaw0/pllms0) 14:12 rgbsel applicable only if aem = 0 (000b). r1/em_a[0]/gp[7]/(aem2) r2/em_ba[0]/gp[6]/(aem1) 011b = rgb666 + lcd_field mode. b2/em_ba[1]/gp[5]/(aem0) venc rgb666 (r2, b2) and lcd_field pins are supported, along with 5 gpio pins (gp[12] and gp[10:7]). the combination of pinmux0 fields rgbsel applicable only if aem = 0 (000b). and aem controls the muxing of these 8 pins. (2) 100b = rgb888 mode. venc rgb888 (g0, b0, r0, g1, b1, r1, r2, b2) pins are supported. applicable only if aem = 0 (000b). 101b through 111b = reserved. chip select 3 select. sub-block 1 00 = gpio pin (gp13) ( default) lcd_oe/ em_cs3/gp[13] 11:10 cs3sel 01 = emifa chip select 3 ( em_cs3) the pinmux0 field cs3sel alone controls the 10 = venc lcd output enable (lcd_oe) muxing of this pin. 11 = reserved chip select 4 select. sub-block 1 00 = gpio pin (gp32) ( default) vsync/ em_cs4/gp[32] 9:8 cs4sel 01 = emifa chip select 4 ( em_cs4) the pinmux0 field cs4sel alone controls the 10 = venc vertical sync (vsync) muxing of this pin. 11 = reserved (1) the aeaw default value is latched at reset from aeaw[2:0] configuration inputs. the latched values are also shown at bootcfg.pllms ( read-only). (2) for the full set of valid configurations of these pins, see section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary. 98 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-19. pinmux0 register bit descriptions (continued) bit field name description pins controlled chip select 5 select. sub-block 1 00 = gpio pin (gp33) ( default) hsync/ em_cs5/gp[33] 7:6 cs5sel 01 = emifa chip select 5 ( em_cs5) the pinmux0 field cs5sel alone controls the 10 = venc horizontal sync (hsync) muxing of this pin. 11 = reserved sub-block 1 vclk/gp[31] yout7/gp[29] yout6/gp[28] yout5/gp[27] venc mode select. yout4/gp[26] yout3/gp[25] 00 = no venc supported. yout2/gp[24] 9 pins function as gpio (gp[31], gp[29:22]). the remaining 8 pins function as yout1/gp[23] gpio/emifa based on aem setting. yout0/gp[22] 01 = 8-bit venc supported. the pinmux0 field vencsel alone controls 5:4 vencsel venc vclk, yout[7:0] functions are pinned out. the remaining 8 pins function the muxing of these 9 pins. as gpio/emifa based on aem setting. cout7/em_d[7]/gp[21] 10 = 16-bit venc supported. cout6/em_d[6]/gp[20] these pins function as venc vclk, yout[7:0], and cout[7:0]. cout5/em_d[5]/gp[19] applicable only if aem = 0 (000b), 3 (011b), 4 (100b). cout4/em_d[4]/gp[18] cout3/em_d[3]/gp[17] 11 = reserved cout2/em_d[2]/gp[16] cout1/em_d[1]/gp[15] cout0/em_d[0]/gp[14 the combination of pinmux fields vencsel and aem controls the muxing of these 8 pins. (1) reserved. for proper device operation, the user should only write "0" to this bit 3 rsv ( default). (1) for the full set of valid configurations of these pins, see section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary. submit documentation feedback device configurations 99
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-19. pinmux0 register bit descriptions (continued) bit field name description pins controlled sub-block 0 em_r/ w/gp[35] em_a[21]/gp[34] em_a[13]/ad25/em_d[0]/gp[51] em_a[14]/ad27/em_d[1]/gp[50] em_a[15]/ad29/em_d[2]/gp[49] em_a[16]/ pgnt/em_d[3]/gp[48] em_a[17]/ad31/em_d[4]/gp[47] em_a[18]/ prst/em_d[5]/gp[46] emifa pinout modes em_a[19]/ preq/em_d[6]/gp[45] this field does not affect the actual emifa operation. it only determines what em_a[20]/ pinta/em_d[7]/gp[44] multiplexed pins in the emifa/vpss block serves as emifa pins. sub-block 1 000b = no emifa mode. cout7/em_d[7]/gp[21] none of the multiplexed pins in the emifa/vpss block serves as emifa pins. cout6/em_d[6]/gp[20] 001b = 8-bit emifa (async) pinout mode 1. cout5/em_d[5]/gp[19] (16m-byte address reach per chip select space). cout4/em_d[4]/gp[18] pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit cout3/em_d[3]/gp[17] emifa (async or nand) + 8-bit venc (vpbe) cout2/em_d[2]/gp[16] cout1/em_d[1]/gp[15] 010b = reserved. cout0/em_d[0]/gp[14] 2:0 aem (1) g0/ em_cs2/gp[12] 011b = 8-bit emifa (async) pinout mode 3. b0/lcd_field/em_a[3]/gp[11] (32k-byte reach per chip select space). r0/em_a[4]/gp[10]/(aeaw2/pllms2) pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit g1/em_a[1]/(ale)/gp[9]/(aeaw1/pllms1) emifa (async or nand) + 16-bit venc (vpbe) b1/em_a[2]/(cle)/gp[8]/(aeaw0/pllms0) r1/em_a[0]/gp[7]/(aem2) 100b = 8-bit emifa (nand) pinout mode 4. r2/em_ba[0]/gp[6]/(aem1) pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit b2/em_ba[1]/gp[5]/(aem0) emifa (nand) + 16-bit venc (vpbe) sub-block3 101b = 8-bit emifa (nand) pinout mode 5. pinout allows up to a maximum of these functions from emifa/vpss block: 8-bit em_a[12]/ pcbe3/gp[89] emifa (nand) + 8-bit venc (vpbe) em_a[11]/ad24/gp[90] em_a[10]/ad23/gp[91] 110b through 111b = reserved em_a[9]/pidsel/gp[92] em_a[8]/ad21/gp[93] em_a[7]/ad22/gp[94] em_a[6]/ad20/gp[95] em_a[5]/ad19/gp[96] the pin mux for these pins are controlled by a combination of aem and other pinmux0 fields, including aeaw, pcien, vencsel, and rgbsel. (2) (1) the aem default value is latched at reset from aem[2:0] configuration inputs. the latched values are also shown at bootcfg.daem ( read-only). (2) for the full set of valid configurations of these pins, see section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary. 100 device configurations submit documentation feedback
3.7.2.2 pinmux1 register description tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the pin multiplexing 1 register (pinmux1) controls the pin multiplexing of all pin mux blocks. the pinmux1 register format is shown in figure 3-13 and the bit field descriptions are given in table 3-20 . some muxed pins are controlled by more than one pinmux bit field. for the combination of pinmux bit fields that control each muxed pin, see section 3.7.3.1 , multiplexed pins on dm6433. 31 26 25 24 23 22 21 20 19 18 17 16 reserved spbk1 spbk0 tim1bk rsv tim0bk r/w-0000 00 r/w-00 r/w-00 r/w-00 r/w-00 r/w-00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pwm1b ckobk rsv ur0fcbk rsv ur0dbk rsv hostbk reserved pcien k r/w-01 r/w-0 r/w-0 r/w-00 r/w-0 r/w-0 r/w-0 r/w-000 r/w-000 r-p legend: r/w = read/write; r = read only; p = specified pin state; - n = value after reset (1) for proper dm6433 device operation, always write a value of "0" to all reserved/rsv bits. figure 3-13. pinmux1 register? 0x01c4 0004 (1) table 3-20. pinmux1 register bit descriptions bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to this bit 31:26 reserved ? ( default). serial port sub-block 1 pin select. selects the function of the multiplexed pins in the serial port sub-block 1. serial port sub-block 1: 00 = gpio mode ( default). axr0[0]/gp[105] pins function as gpio (gp[110:105]). aclkx0/gp[106] 25:24 spbk1 01 = reserved. afsx0/gp[107] ahclkx0/gp[108] 10 = mcasp0 transmit and 1 serializer. amutein0/gp[109] pins function as mcasp0: axr0[0], aclkx0, afsx0, ahclkx0, amutein0, amute0/gp[110] and amute0. 11 = reserved. serial port sub-block 0 pin select. selects the function of the multiplexed pins in the serial port sub-block 0. 00 = gpio mode ( default). serial port sub-block 0: pins function as gpio (gp[104:99]). aclkr0/clkx0/gp[99] afsr0/dr0/gp[100] 01 = mcbsp0 mode. 23:22 spbk0 ahclkr0/clkr0/gp[101] pins function as mcbsp0 clkx0, fsx0, dx0, clkr0, fsr0, and dr0. axr0[3]/fsr0/gp[102] axr0[2]/fsx0/gp[103] 10 = mcasp0 receive and 3 serializers. axr0[1]/dx0/gp[104] pins function as mcasp0 aclkr0, afsr0, ahclkr0, axr0_3, axr0_2, and axr0_1. 11 = reserved timer1 block pin select. selects the function of the multiplexed pins in thetimer1 block. 00 = gpio mode ( default). pins function as gpio (gp[56:55]). timer1 block: 21:20 tim1bk tinp1l/gp[56] 01 = timer1 mode. tout1l/gp[55] pins function as timer1 tinp1l and tout1l. 10 = reserved. 11 = reserved. reserved. for proper device operation, the user should only write "0" to this bit 19:18 rsv ? ( default). submit documentation feedback device configurations 101
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-20. pinmux1 register bit descriptions (continued) bit field name description pins controlled timer0 block pin select. selects the function of the multiplexed pins in the timer0 block. 00 = gpio mode ( default). pins function as gpio (gp[98:97]). timer0 block: 01 = timer0 mode. 17:16 tim0bk tinp0l/gp[98] pins function as timer0 tinp0l and tout0l. clks0/tout0l/gp[97] 10 = reserved. 11 = mcbsp0 external clock source + timer0 input mode. pins function as mcbsp0 external clock source clks0, and timer0 input tinp0l. clkout block pin select. selects the function of the multiplexed pins in the clkout block. 00 = gpio mode. pin functions as gpio (gp[84]). clkout block: 15:14 ckobk 01 = clkout mode ( default). clkout0/pwm2/gp[84] pin functions as device clock output clkout0, sourced from pllc1 obsclk. 10 = pwm2 mode. pin functions as pwm2. 11 = reserved reserved. for proper device operation, the user should only write "0" to this bit 13 rsv ? ( default). pwm1 block pin select. selects the function of the multiplexed pins in the pwm1 block. 0 = gpio mode ( default). pwm1 block: 12 pwm1bk pin functions as gpio (gp[4]). gp[4]/pwm1 1 = pwm1 mode. pin functions as pwm1. uart0 flow control block pin select. selects the function of the multiplexed pins in the uart0 flow control block. 00 = gpio mode ( default). pins function as gpio (gp[88:87]). uart0 flow control block: 11:10 ur0fcbk 01 = uart0 flow control mode. ucts0/gp[87] pins function as uart0 flow control ucts0 and urts0. urts0/pwm0/gp[88] 10 = pwm0 + gpio mode. pins function as pwm0 and gpio (gp[87]). 11 = reserved reserved. for proper device operation, the user should only write "0" to this bit 9 rsv ? ( default). uart0 data block pin select. selects the function of the multiplexed pins in the uart0 data block. uart0 data block: 0 = gpio mode ( default). 8 ur0dbk urxd0/gp[85] pins function as gpio (gp[86:85]). utxd0/gp[86] 1 = uart0 data mode. pins function as uart0 data urxd0 and utxd0. 102 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-20. pinmux1 register bit descriptions (continued) bit field name description pins controlled reserved. for proper device operation, the user should only write "0" to this bit 7 rsv ? ( default). host block: vlynq_clock/pciclk/gp[57] host block pin select. hd0/vlynq_scrun/ad18/gp[58] if emac opertaion is desired, emac must be placed in reset before hd1/vlynq_rxd0/ad16/gp[59] programminng pinmux1 hostbk to select emac pins. hd2/vlynq_rxd1/ad17/gp[60] hd3/vlynq_rxd2/ pcbe2/gp[61] pcien = 0 and hostbk = 000: gpio mode ( default if pcien = 0). hd4/vlynq_rxd3/ pframe/gp[62] pins function as gpio (gp[83:57]). hd5/vlynq_txd0/ pirdy/gp[63] hd6/vlynq_txd1/ ptrdy/gp[64] pcien = 0 and hostbk = 001: hpi + 1 gpio mode. hd7/vlynq_txd2/ pdevsel/gp[65] pins function as hpi and gpio (gp[57]). hd8/vlynq_txd3/ pperr/gp[66] pcien = 0 and hostbk = 010: vlynq + 17 gpio mode. hd9/mcol/ pstop/gp[67] pins function as vlynq (vlynq_clock, vlynq_scrun, vlynq_rxd[3:0], hd10/mcrs/ pserr/gp[68] vlynq_txd[3:0]), and gp[83:67]. hd11/mtxd3/ pcbe1/gp[69] hd12/mtxd2/ppar/gp[70] pcien = 0 and hostbk = 011: vlynq + mii + mdio mode. 6:4 hostbk hd13/mtxd1/ad14/gp[71] pins function as vlynq (vlynq_clock, vlynq_scrun, vlynq_rxd[3:0], hd14/mtxd0/ad15/gp[72] vlynq_txd[3:0]), mii (txclk, crs, col, txd[3:0], rxvd, txen, rxer, hd15/mtxclk/ad12/gp[73] rxclk, rxd[3:0]), and mdio (mdio, mdc). hhwil/mrxdv/ad13/gp[74] hcntl1/mtxen/ad11/gp[75] pcien = 0 and hostbk = 100: mii + mdio +10 gpio mode. hcntl0/mrxer/ad10/gp[76] pins function as mii (txclk, crs, col, txd[3:0], rxvd, txen, rxer, hr/ w/mrxclk/ad8/gp[77] rxclk, rxd[3:0]), mdio (mdio, mdc), and gp[66:57]. hds2/mrxd0/ad9/gp[78] hds1/mrxd1/ad7/gp[79] pcien = 1 and hostbk = 000: pci mode ( default if pcien = 1). hrdy/mrxd2/ pcbe0/gp[80] pins function as pci pins: pciclk, pcbe2, pcbe1, pcbe0, pframe, hcs/mdclk/ad5/gp[81] pidrdy, ptrdy, pdevsel, pper, pstop, pserr, ppar, ad[18:5], and hint/mrxd3/ad6/gp[82] ad03. has/mdio/ad3/gp[83] all other pcien and hostbk combinations reserved. the combination of pinmux1 fields pcien and hostbk select the function of these 27 pins. reserved. for proper device operation, the user should only write "0" to this bit 3:1 reserved ? ( default). submit documentation feedback device configurations 103
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-20. pinmux1 register bit descriptions (continued) bit field name description pins controlled host block: see list of 27 pins in hostbk bit field description pci data block: ad26 ad28 ad30 gpio block: ad0/gp[0] ad1/gp[1] pci enable. ad2/gp[2] ad4/gp[3] the pinmux1.pcien reflects the state of the pcien pin. pinmux1.pcien is read only and cannot be modified by software. for proper device emifa/vpss sub-block 0*: operation, the user must hold the desired setting at the pcien pin em_a[13]/ad25/em_d[0]/gp[51] throughout device operation. em_a[14]/ad27/em_d[1]/gp[50] em_a[15]/ad29/em_d[2]/gp[49] pcien = 0: no pci supported. internal pullup/pulldown (ipu/ipd) on these pins em_a[16]/ pgnt/em_d[3]/gp[48] are enabled. em_a[17]/ad31/em_d[4]/gp[47] for pci multiplexed pins in the gpio block, when pcien = 0, the pins function em_a[18]/ prst/em_d[5]/gp[46] as gpio (gp[3:0]). em_a[19]/ preq/em_d[6]/gp[45] 0 pcien for pci multiplexed pins in the host block, refer to pinmux1.hostbk field for em_a[20]/ pinta/em_d[7]/gp[44] the actual pin functions. emifa/vpss sub-block 3*: for pci multiplexed pins in the emifa/vpss block, refer to pinmux0.aem and em_a[12]/ pcbe3/gp[89] aeaw fields for the actual pin functions. em_a[11]/ad24/gp[90] for pci pins in the pci data block, when pcien = 0, the pins have no function em_a[10]/ad23/gp[91] and should be left unconnected. em_a[9]/pidsel/gp[92] pcien = 1: pci supported. internal pullup/pulldown (ipu/ipd) on all pci pins em_a[8]/ad21/gp[93] are disabled. em_a[7]/ad22/gp[94] em_a[6]/ad20/gp[95] all pins function as pci pins. em_a[5]/ad19/gp[96] applicable only for pinmux0.aem = 000b or 101b. the pin mux for the emifa/vpss sub-block 0 and emifa/vpss sub-block 3 pins are controlled by a combination of pcien and other pinmux0/1 fields, including hostbk, aem, and aeaw. see section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary, for the full set of valid configurations of emifa/vpss block pins. for the full set of valid configurations of host block pins, see section 3.7.3.3 , host block muxing. device configurations 104 submit documentation feedback
3.7.3 pin multiplexing details 3.7.3.1 multiplexed pins on dm6433 tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this section discusses how to program each pin mux block to select the desired peripheral functions. the following steps can be used to determine pin muxing suitable for the application: 1. understand the major configuration choices available for the specific application. a. device major configuration choices: figure 3-11 shown in section 3.7 , multiplexed pin configurations, provides a high-level view of the device pin muxing and can be used to determine the possible mix of peripheral options for a specific application. b. emifa/vpss block major configuration choices: the emifa/vpss block features extensive pin multiplexing to accommodate a variety of applications. in addition to figure 3-11 , section 3.7.3.13 , emifa/vpss block muxing, provides more details on the major configuration choices for this block. 2. see section 3.7.3.1 , multiplexed pins on dm6433, for a summary of all the multiplexed pins on this device and the pin mux group they belong to. 3. refer to the individual pin mux sections (section 3.7.3.3 , host block muxing to section 3.7.3.13 , emifa/vpss block muxing) for pin muxing details for a specific pin mux block. a. for peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that peripheral in all relevant pin mux blocks. for more details, see section 3.7.3.2 , peripherals spanning multiple pin mux blocks . for details on pinmux0 and pinmux1 registers, see section 3.7.2 . table 3-21 summarizes all of the multiplexed pins on dm6433, the pin mux group for each pin, and the pinmux register fields that control the pin. for pin mux details, see the specific pin mux group section (section 3.7.3.3 , host block muxing to section 3.7.3.13 , emifa/vpss block muxing). for a description of the pinmux register fields, see section 3.7.2 . table 3-21. multiplexed pins on dm6433 signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. gp[54] a14 a18 emifa/vpss sub-block 0 gp[54:52] are standalone pins. they are not muxed with any other functions. they gp[53] a13 a17 emifa/vpss sub-block 0 are included in this table because they are grouped in the emifa/vpss gp[52] a15 a19 emifa/vpss sub-block 0 sub-block 0. em_a[13]/ad25/ b10 a12 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[0]/gp[51] em_a[14]/ad27/ a10 a13 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[1]/gp[50] em_a[15]/ad29/ b11 c13 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[2]/gp[49] em_a[16]/ pgnt/ c11 b13 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[3]/gp[48] em_a[17]/ad31/ a11 b14 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[4]/gp[47] em_a[18]/ prst/ d11 a14 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[5]/gp[46] em_a[19]/ preq/ b12 c14 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[6]/gp[45] em_a[20]/ pinta/ c12 c15 emifa/vpss sub-block 0 pcien, aem, aeaw em_d[7]/gp[44] submit documentation feedback device configurations 105
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-21. multiplexed pins on dm6433 (continued) signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. gp[43] a12 a15 emifa/vpss sub-block 0 gp[42] b13 b15 emifa/vpss sub-block 0 gp[41] c13 b16 emifa/vpss sub-block 0 gp[43:36] are standalone pins. they are not muxed with any other functions. they gp[40] d14 c18 emifa/vpss sub-block 0 are included in this table because they gp[39] b14 a16 emifa/vpss sub-block 0 are grouped in the emifa/vpss sub-block 0. gp[38] c14 b17 emifa/vpss sub-block 0 gp[37] b15 b18 emifa/vpss sub-block 0 gp[36] c15 b19 emifa/vpss sub-block 0 em_r/ w/gp[35] d13 c17 emifa/vpss sub-block 0 aem em_a[21]/gp[34] d12 c16 emifa/vpss sub-block 0 aem hsync/ em_cs5/gp[33] f19 j22 emifa/vpss sub-block 1 cs5sel vsync/ em_cs4/gp[32] e19 h22 emifa/vpss sub-block 1 cs4sel vclk/gp[31] d19 g22 emifa/vpss sub-block 1 vencsel vpbeclk/gp[30] g19 k22 emifa/vpss sub-block 1 vpbecken yout7/gp[29] h15 k21 emifa/vpss sub-block 1 vencsel yout6/gp[28] h16 j21 emifa/vpss sub-block 1 vencsel yout5/gp[27] h17 l19 emifa/vpss sub-block 1 vencsel yout4/gp[26]/(fastboot) g17 k19 emifa/vpss sub-block 1 vencsel yout3/gp[25]/(bootmode3) g16 h21 emifa/vpss sub-block 1 vencsel yout2/gp[24]/(bootmode2) g15 l20 emifa/vpss sub-block 1 vencsel yout1/gp[23]/(bootmode1) f15 k20 emifa/vpss sub-block 1 vencsel yout0/gp[22]/(bootmode0) f18 j20 emifa/vpss sub-block 1 vencsel cout7/em_d[7]/gp[21] f17 h20 emifa/vpss sub-block 1 aem, vencsel cout6/em_d[6]/gp[20] f16 f21 emifa/vpss sub-block 1 aem, vencsel cout5/em_d[5]/gp[19] e17 f22 emifa/vpss sub-block 1 aem, vencsel cout4/em_d[4]/gp[18] e18 g21 emifa/vpss sub-block 1 aem, vencsel cout3/em_d[3]/gp[17] e16 f20 emifa/vpss sub-block 1 aem, vencsel cout2/em_d[2]/gp[16] d17 e22 emifa/vpss sub-block 1 aem, vencsel cout1/em_d[1]/gp[15] d18 g20 emifa/vpss sub-block 1 aem, vencsel cout0/em_d[0]/gp[14] d16 e21 emifa/vpss sub-block 1 aem, vencsel lcd_oe/ em_cs3/gp[13] c18 d22 emifa/vpss sub-block 1 cs3sel g0/ em_cs2/gp[12] c19 c22 emifa/vpss sub-block 1 aem, rgbsel b0/lcd_field/em_a[3]/gp[11] b18 d21 emifa/vpss sub-block 1 aem, rgbsel r0/em_a[4]/gp[10]/(aeaw2/pllms2) a17 b21 emifa/vpss sub-block 1 aem, rgbsel g1/em_a[1]/(ale)/gp[9]/ a16 b20 emifa/vpss sub-block 1 aem, rgbsel (aeaw1/pllms1) b1/em_a[2]/(cle)/gp[8]/ b16 a20 emifa/vpss sub-block 1 aem, rgbsel (aeaw0/pllms0) r1/em_a[0]/gp[7]/(aem2) b17 c21 emifa/vpss sub-block 1 aem, rgbsel r2/em_ba[0]/gp[6]/(aem1) c17 e20 emifa/vpss sub-block 1 aem, rgbsel b2/em_ba[1]/gp[5]/(aem0) c16 c20 emifa/vpss sub-block 1 aem, rgbsel em_a[12]/ pcbe3/gp[89] d10 b12 emifa/vpss sub-block 3 pcien, aem em_a[11]/ad24/gp[90] c10 c12 emifa/vpss sub-block 3 pcien, aem em_a[10]/ad23/gp[91] a9 b11 emifa/vpss sub-block 3 pcien, aem em_a[9]/pidsel/gp[92] d9 c11 emifa/vpss sub-block 3 pcien, aem em_a[8]/ad21/gp[93] b9 a11 emifa/vpss sub-block 3 pcien, aem device configurations 106 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-21. multiplexed pins on dm6433 (continued) signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. em_a[7]/ad22/gp[94] c9 c10 emifa/vpss sub-block 3 pcien, aem em_a[6]/ad20/gp[95] d8 b10 emifa/vpss sub-block 3 pcien, aem em_a[5]/ad19/gp[96] b8 a10 emifa/vpss sub-block 3 pcien, aem vlynq_clock/pciclk/gp[57] a7 a8 host block pcien, hostbk hd0/vlynq_scrun/ad18/gp[58] c8 b9 host block pcien, hostbk hd1/vlynq_rxd0/ad16/gp[59] d7 c9 host block pcien, hostbk hd2/vlynq_rxd1/ad17/gp[60] a8 a9 host block pcien, hostbk hd3/vlynq_rxd2/ pcbe2/gp[61] b7 b8 host block pcien, hostbk hd4/vlynq_rxd3/ pframe/gp[62] c7 c8 host block pcien, hostbk hd5/vlynq_txd0/ pirdy/gp[63] a6 a7 host block pcien, hostbk hd6/vlynq_txd1/ ptrdy/gp[64] d6 c7 host block pcien, hostbk hd7/vlynq_txd2/ pdevsel/gp[65] b6 b7 host block pcien, hostbk hd8/vlynq_txd3/ pperr/gp[66] a5 a6 host block pcien, hostbk hd9/mcol/ pstop/gp[67] c6 c6 host block pcien, hostbk hd10/mcrs/ pserr/gp[68] b5 b6 host block pcien, hostbk hd11/mtxd3/ pcbe1/gp[69] c5 a5 host block pcien, hostbk hd12/mtxd2/ppar/gp[70] d5 c5 host block pcien, hostbk hd13/mtxd1/ad14/gp[71] b4 b4 host block pcien, hostbk hd14/mtxd0/ad15/gp[72] d4 b5 host block pcien, hostbk hd15/mtxclk/ad12/gp[73] a4 a4 host block pcien, hostbk hhwil/mrxdv/ad13/gp[74] c4 d3 host block pcien, hostbk hcntl1/mtxen/ad11/gp[75] d3 c4 host block pcien, hostbk hcntl0/mrxer/ad10/gp[76] b3 b2 host block pcien, hostbk hr/ w/mrxclk/ad8/gp[77] a3 a3 host block pcien, hostbk hds2/mrxd0/ad9/gp[78] c3 c2 host block pcien, hostbk hds1/mrxd1/ad7/gp[79] b2 b3 host block pcien, hostbk hrdy/mrxd2/ pcbe0/gp[80] d2 c3 host block pcien, hostbk hcs/mdclk/ad5/gp[81] c1 d1 host block pcien, hostbk hint/mrxd3/ad6/gp[82] c2 d2 host block pcien, hostbk has/mdio/ad3/gp[83] d1 c1 host block pcien, hostbk ad0/gp[0] e1 e1 gpio block pcien ad1/gp[1] e2 e2 gpio block pcien ad2/gp[2] e3 f1 gpio block pcien ad4/gp[3] e4 f2 gpio block pcien gp[4]/pwm1 f3 f3 pwm1block pwm1bk aclkr0/clkx0/gp[99] h1 j1 serial port sub-block 0 spbk0 afsr0/dr0/gp[100] h4 k3 serial port sub-block 0 spbk0 ahclkr0/clkr0/gp[101] j2 k1 serial port sub-block 0 spbk0 axr0[3]/fsr0/gp[102] g4 j3 serial port sub-block 0 spbk0 axr0[2]/fsx0/gp[103] h3 j2 serial port sub-block 0 spbk0 axr0[1]/dx0/gp[104] j3 k2 serial port sub-block 0 spbk0 axr0[0]/gp[105] h2 h2 serial port sub-block 1 spbk1 aclkx0/gp[106] f1 g1 serial port sub-block 1 spbk1 afsx0/gp[107] g2 g2 serial port sub-block 1 spbk1 ahclkx0/gp[108] g1 h1 serial port sub-block 1 spbk1 submit documentation feedback device configurations 107
3.7.3.2 peripherals spanning multiple pin mux blocks tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-21. multiplexed pins on dm6433 (continued) signal pinmux description zwt zdu name pinmux group controlled by pinmux bit fields no. no. amutein0/gp[109] f2 g3 serial port sub-block 1 spbk1 amute0/gp[110] g3 h3 serial port sub-block 1 spbk1 tinp1l/gp[56] l4 p3 timer 1 block tim1bk tout1l/gp[55] k4 n3 timer 1 block tim1bk tinp0l/gp[98] k2 l2 timer 0 block tim0bk clks0/tout0l/gp[97] j4 l3 timer 0 block tim0bk urxd0/gp[85] l2 m2 uart0 data block ur0dbk utxd0/gp[86] k3 n1 uart0 data block ur0dbk ucts0/gp[87] l1 p1 uart0 flow control block ur0fcbk urts0/pwm0/gp[88] l3 m3 uart0 flow control block ur0fcbk clkout0/pwm2/gp[84] m1 r1 clkout block ckobk note: pinmux groups emifa/vpss sub-block 2 and pci data block are not shown in the above table because there is no actual pin multiplexing in those blocks. but these two blocks are still considered "pin mux blocks" because they contain some of the pins necessary for emifa and pci, respectively. the pins in these blocks are as follows: emifa/vpss sub-block 2 ? em_wait/(rdy/ bsy) ? em_oe ? em_we some peripherals span multiple pin mux blocks. to use these peripherals, they must be selected in all of the relevant pin mux blocks. the following is the list of peripherals that span multiple pin mux blocks: pci: pci pins span across the host block, emifa/vpss block sub-block 0 and sub-block 3, pci data block, and gpio block. to select pci pins, program pinmux registers as follows: ? host block: pcien = 1, hostbk = 000 ? emifa/vpss block: select either major configuration option f or g. for more details on the pinmux settings associated with major configuration options f or g, see section 3.7.3.13 , emifa/vpss block muxing. ? pci data block: pcien = 1 ? gpio block: pcien = 1 mcbsp0: six mcbsp0 pins are located in the serial port sub-block 0, but the clks0 pin is muxed in the timer0 block. to select mcbsp0 pins, program pinmux registers as follows: ? serial port sub-block 0: spbk0 = 01 ? timer0 block: if clks0 pin is desired, program tim0bk = 10 or 11. uart0: the two uart0 data pins are located in the uart0 data block, but the two uart0 flow control pins are located in the uart0 flow control block. to select uart0, program pinmux registers as follows: ? uart0 data block: ur0bk = 1 ? uart0 flow control block: if flow control pins are desired, program ur0fcbk = 01. 108 device configurations submit documentation feedback
3.7.3.3 host block muxing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this block of 27 pins consists of pci, hpi, vlynq, emac, mdio, and gpio muxed pins. the following register fields select the pin functions in the host block: pinmux1.pcien pinmux1.hostbk table 3-22 summarizes the 27 pins in the host block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. submit documentation feedback device configurations 109
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-22. host block muxed pins selection multiplexed functions signal name hpi emac/mdio vlynq pci gpio function select function select function select function select function select pcien = 0, and hostbk = 000 vlynq_clock/pciclk/gp[57] ? ? ? ? vlynq_clock pciclk gp[57] or hostbk = 001 or hostbk = 100 hd0/vlynq_scrun/ad18/gp[58] hd0 ? ? vlynq_scrun ad18 gp[58] pcien = 0, hd1/vlynq_rxd0/ad16/gp[59] hd1 ? ? vlynq_rxd0 and ad16 gp[59] hostbk = 010 hd2/vlynq_rxd1/ad17/gp[60] hd2 ? ? vlynq_rxd1 ad17 gp[60] or pcien = 0, hostbk = 011 hd3/vlynq_rxd2/ pcbe2/gp[61] hd3 ? ? vlynq_rxd2 pcbe2 gp[61] and hd4/vlynq_rxd3/ pframe/gp[62] hd4 ? ? vlynq_rxd3 pframe gp[62] hostbk = 000 or hd5/vlynq_txd0/ pirdy/gp[63] hd5 ? ? vlynq_txd0 pirdy gp[63] hostbk = 100 hd6/vlynq_txd1/ ptrdy/gp[64] hd6 ? ? vlynq_txd1 ptrdy gp[64] hd7/vlynq_txd2/ pdevsel/gp[65] hd7 ? ? vlynq_txd2 pdevsel gp[65] hd8/vlynq_txd3/ pperr/gp[66] hd8 ? ? vlynq_txd3 pperr gp[66] hd9/mcol/ pstop/gp[67] hd9 mcol ? ? pstop gp[67] pcien = 1, hd10/mcrs/ pserr/gp[68] hd10 mcrs ? ? pserr gp[68] and hostbk = 000 hd11/mtxd3/ pcbe1/gp[69] hd11 mtxd3 ? ? pcbe1 gp[69] pcien = 0, hd12/mtxd2/ppar/gp[70] hd12 mtxd2 ? ? ppar gp[70] and hd13/mtxd1/ad14/gp[71] hd13 mtxd1 ? ? ad14 gp[71] hostbk = 001 hd14/mtxd0/ad15/gp[72] hd14 mtxd0 ? ? ad15 gp[72] hd15/mtxclk/ad12/gp[73] hd15 mtxclk ? ? ad12 gp[73] pcien = 0, pcien = 0, hhwil/mrxdv/ad13/gp[74] hhwil mrxdv ? ? ad13 gp[74] and and hcntl1/mtxen/ad11/gp[75] hcntl1 mtxen hostbk = 011 ? ? ad11 gp[75] hostbk = 000 or or hcntl0/mrxer/ad10/gp[76] hcntl0 mrxer ? ? ad10 gp[76] hostbk = 100 hostbk = 010 hr/ w/mrxclk/ad8/gp[77] hr/ w mrxclk ? ? ad8 gp[77] hds2/mrxd0/ad9/gp[78] hds2 mrxd0 ? ? ad9 gp[78] hds1/mrxd1/ad7/gp[79] hds1 mrxd1 ? ? ad7 gp[79] hrdy/mrxd2/ pcbe0/gp[80] hrdy mrxd2 ? ? pcbe0 gp[80] hcs/mdclk/ad5/gp[81] hcs mdclk ? ? ad5 gp[81] hint/mrxd3/ad6/gp[82] hint mrxd3 ? ? ad6 gp[82] has/mdio/ad3/gp[83] has mdio ? ? ad3 gp[83] 110 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, pci pins span across the following pin mux blocks: host block, emifa/vpss block sub-block 0 and sub-block 3, pci data block, and gpio block. for proper pci operation, pci must be selected in all of these pin mux blocks. table 3-23 provides a different view of the host block pin muxing, showing the host block function based on pinmux1 settings. the selection options are also shown pictorially in figure 3-11 . if emac operation is desired, emac must be placed in reset before programming pinmux1.hostbk to select emac pins. table 3-23. host block function selection pinmux1 setting block function resulting pin functions pcien (1) hostbk pci: pciclk, pcbe2, pcbe1, pcbe0, pframe, pidrdy, ptrdy, pci 1 000 pdevsel, pstop, pper, pserr, ppar, ad[18:05], ad[03] (default if pcien = 1) internal pullup/pulldown on all these pins are disabled. 1 001 to 111 reserved reserved gpio (27) 0 000 gpio: gp[83:57] (default if pcien = 0) hpi: hhwil, hcntl[1:0], hr/ w, hds2, hds1, hrdy, hcs, hint, has, 0 001 hpi + gpio (1) hd[15:0] gpio: gp[57] vlynq: vlynq_clock, vlynq_scrun, vlynq_rxd[3:0], vlynq_txd[3:0] 0 010 vlynq + gpio (17) gpio: gp[83:67] vlynq: vlynq_clock, vlynq_scrun, vlynq_rxd[3:0], vlynq_txd[3:0] emac (mii): txclk, crs, col, txd[3:0], rxdv, txen, rxer, rxclk, 0 011 vlynq + emac (mii) + mdio rxd[3:0] mdio: mdc, mdio if emac operation is desired, emac must be placed in reset before programming pinmux1.hostbk to select emac pins. emac (mii): txclk, crs, col, txd[3:0], rxdv, txen, rxer, rxclk, rxd[3:0] mdio: mdc, mdio 0 100 emac (mii) + mdio + gpio (10) gpio: gp[66:57] if emac operation is desired, emac must be placed in reset before programming pinmux1.hostbk to select emac pins. 0 101 to 111 reserved reserved (1) if pcien = 1, the internal pullup/pulldown on all host block pins are disabled. if pcien = 0, the internal pullup/pulldown on all host block pins are enabled. the pinmux1.pcien field is read-only, and its setting is determined by the pcien configuration pin. based on the pcien configuration pin setting, the 27 pins in the host block defaults to either pci or gpio function. in addition, the vdd3p3v_pwdn.host field determines the power state of the host block pins. the host block pins default to powered up. for more details on the vdd3p3v_pwdn.host field, see section 3.2 , power considerations. submit documentation feedback device configurations 111
3.7.3.4 pci data block tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com this block of 3 pins consists of 3 pci address/data pins?ad30, ad28, ad26. the pinmux1.pcien register field affects the pin functions in the pci data block. as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, pci pins span across the following pin mux blocks: host block, emifa/vpss block sub-block 0 and sub-block 3, pci data block, and gpio block. for proper pci operation, pci must be selected in all of these pin mux blocks. the 3 pins in the pci data block are not muxed with any other peripherals. however, the pinmux1.pcien field controls the internal pullup/pulldown resistors on these pins. for pci operation (pcien = 1), the internal pullup/pulldown resistors are disabled. if the device does not support pci (pcien = 0), the internal pullup/pulldown resistors on these pins are enabled so that the user can leave these pins unconnected on the board. table 3-24 shows the host block pin selection based on pinmux1.pcien setting. table 3-24. pci data block pin control pinmux1.pcien block function resulting pin functions no connect pins no connect pins 0 (default if pcien = 0) internal pullup/pulldown enabled. leave these three pins unconnected on the board. pci 1 pci: ad26, ad28, ad30 (default if pcien = 1) device configurations 112 submit documentation feedback
3.7.3.5 gpio block muxing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this block of 4 pins consists of pci and gpio muxed pins. the pinmux1.pcien register field selects the pin functions in the gpio block. table 3-25 summarizes the 4 pins in the gpio block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-25. gpio block muxed pins selection multiplexed functions signal pci gpio name function select function select ad0/gp[0] ad0 gp[0] ad1/gp[1] ad1 gp[1] pcien = 1 (1) pcien = 0 (1) ad2/gp[2] ad2 gp[2] ad4/gp[3] ad4 gp[3] (1) if pcien = 1, the internal pullup/pulldown on all gpio block pins are disabled. if pcien = 0, the internal pullup/pulldown on all gpio block pins are enabled. as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, pci pins span across the following pin mux blocks: host block, emifa/vpss block sub-block 0 and sub-block 3, pci data block, and gpio block. for proper pci operation, pci must be selected in all of these pin mux blocks. table 3-26 provides a different view of the gpio block pin muxing, showing the gpio block function based on pinmux1.pcien setting. the selection options are also shown pictorially in figure 3-11 . table 3-26. gpio block function selection pinmux1.pcien block function resulting pin functions pci 0 pci: ad0, ad1, ad2, ad4 (default if pcien = 1) gpio (4) 1 gpio: gp[3:0] (default if pcien = 0) the pinmux1.pcien field is read-only, and its setting is determined by the pcien configuration pin. based on the pcien configuration pin setting, the 4 pins in the gpio block defaults to either pci or gpio function. in addition, the vdd3p3v_pwdn.gpio field determines the power state of the gpio block pins. the gpio block pins default to powered up. for more details on the vdd3p3v_pwdn.gpio field, see section 3.2 , power considerations. submit documentation feedback device configurations 113
3.7.3.6 uart0 data block muxing 3.7.3.7 uart0 flow control block tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com this block of 2 pins consists of uart0 data and gpio muxed pins. the pinmux1.ur0dbk register field select the pin functions in the uart0 data block. table 3-27 summarizes the 2 pins in the uart0 data block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-27. uart0 data block muxed pins selection multiplexed functions signal uart0 gpio name function select function select urxd0/gp[85] urxd0 gp[85] ur0dbk = 1 ur0dbk = 0 utxd0/gp[86] utxd0 gp[86] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the uart0 pins span across two pin mux blocks: uart0 data block, and uart0 flow control block. for proper uart0 operation, the two pins in the uart0 data block must be configured for uart0 data functions. the two pins in the uart0 flow control block are optional. table 3-28 provides a different view of the uart0 data block pin muxing, showing the uart0 data block function based on pinmux1.ur0dbk setting. the selection options are also shown pictorially in figure 3-11 . table 3-28. uart0 data block function selection pinmux1.ur0dbk block function resulting pin functions 0 gpio (2) ( default) gpio: gp[86:85] 1 uart0 data uart0: urxd0, utxd0 in addition, the vdd3p3v_pwdn.ur0dat field determines the power state of the uart0 data block pins. the uart0 data block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.ur0dat = 0 to power up the pins. for more details on the vdd3p3v_pwdn.ur0dat field, see section 3.2 , power considerations. the uart0 data block features internal pullup resistors, which matches the uart inactive polarity. this block of 2 pins consists of uart0 flow control, pwm0, and gpio muxed pins. the pinmux1.ur0fcbk register field selects the pin functions in the uart0 flow control block. table 3-29 summarizes the 2 pins in the uart0 flow control block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-29. uart0 flow control block muxed pins selection multiplexed functions signal uart0 pwm0 gpio name function select function select function select ucts0/ ucts0 ? ? gp[87] ur0fcbk = 00/10 gp[87] ur0fcbk = 01 urts0/ pwm0/ urts0 pwm0 ur0fcbk = 10 gp[88] ur0fcbk = 00 gp[88] device configurations 114 submit documentation feedback
3.7.3.8 timer0 block tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the uart0 pins span across two pin mux blocks: uart0 data block, and uart0 flow control block. for proper uart0 operation, the two pins in the uart0 data block must be configured for uart0 data functions. the two pins in the uart0 flow control block are optional. table 3-30 provides a different view of the uart0 flow control block pin muxing, showing the uart0 flow control block function based on pinmux1.ur0fcbk setting. the selection options are also shown pictorially in figure 3-11 . table 3-30. uart0 flow control block function selection pinmux1.ur0fcbk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[88:87] 01 uart0 flow control uart0: ucts0, urts0 pwm0: pwm0 10 pwm0 + gpio (1) gpio: gp[87] 11 reserved reserved in addition, the vdd3p3v_pwdn.ur0fc field determines the power state of the uart0 flow control block pins. the uart0 flow control block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.ur0fc = 0 to power up the pins. for more details on the vdd3p3v_pwdn.ur0fc field, see section 3.2 , power considerations. the uart0 flow control block features internal pullup resistors, which matches the uart inactive polarity. this block of 2 pins consists of timer0, mcbsp0, and gpio muxed pins. the pinmux1.tim0bk register field selects the pin functions in the timer0 block. table 3-31 summarizes the 2 pins in the timer0 block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-31. timer0 block muxed pins selection multiplexed functions signal mcbsp timer0 gpio name function select function select function select tinp0l/ ? ? tinp0l tim0bk = 01/11 gp[98] gp[98] tim0bk = 00 clks0/ tout0l/ clks0 tim0bk = 11 tout0l tim0bk = 01 gp[97] gp[97] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the mcbsp0 pins span across two pin mux blocks: serial port sub-block0, and timer0 block. for proper mcbsp0 operation, the serial port sub-block0 must be programmed to select mcbsp0 function. the mcbsp0 clks0 pin in the timer0 block is optional for mcbsp0 operation. clks0 is only needed if you desire using clks0 as an external clock source to the mcbsp0 internal sample rate generator. submit documentation feedback device configurations 115
3.7.3.9 timer1 block tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-32 provides a different view of the timer0 block pin muxing, showing the timer0 block function based on pinmux1.tim0bk setting. the selection options are also shown pictorially in figure 3-11 . table 3-32. timer0 block function selection pinmux1.tim0bk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[98:97] 01 timer0 timer0: tinp0l, tout0l 10 reserved reserved mcbsp0 external clock source, mcbsp0: clks0 11 timer0 input timer0: tinp0l in addition, the vdd3p3v_pwdn.timer0 field determines the power state of the timer0 block pins. the timer0 block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.timer0 = 0 to power up the pins. for more details on the vdd3p3v_pwdn.timer0 field, see section 3.2 , power considerations. this block of 2 pins consists of timer1 and gpio muxed pins. the pinmux1.tim1bk register field selects the pin functions in the timer1 block. table 3-33 summarizes the 2 pins in the timer1 block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-33. timer1 block muxed pins selection multiplexed functions signal timer1 gpio name function select function select tinp1l/ tinp1l gp[56] gp[56] tim1bk = 01 tim1bk = 00 tout1l/ tout1l gp[55] gp[55] table 3-34 provides a different view of the timer1 block pin muxing, showing the timer1 block function based on pinmux1.tim1bk setting. the selection options are also shown pictorially in figure 3-11 . table 3-34. timer1 block function selection pinmux1.tim1bk block function resulting pin functions 00 gpio (2) ( default) gpio: gp[56:55] 01 timer1 timer1: tinp1l, tout1l 10 reserved reserved 11 reserved reserved in addition, the vdd3p3v_pwdn.timer1 field determines the power state of the timer1 block pins. the timer1 block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.timer1 = 0 to power up the pins. for more details on the vdd3p3v_pwdn.timer1 field, see section 3.2 , power considerations. the timer1 block features internal pullup resistors. device configurations 116 submit documentation feedback
3.7.3.10 serial port block tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this block of 12 pins consists of mcasp0, mcbsp0, and gpio muxed pins. the following register fields select the pin functions in the serial port block: pinmux1.spbk0 pinmux1.spbk1 the serial port block is further subdivided into these sub-blocks: serial port sub-block 0: mcbsp0, part of mcasp0, gpio. serial port sub-block 1: part of mcasp0, gpio. table 3-35 summarizes the 12 pins in the serial port block, the multiplexed function on each pin, and the pinmux configurations to select the corresponding function. table 3-35. serial port block muxed pins selection multiplexed functions signal name mcasp0 mcbsp0 gpio function select function select function select serial port sub-block 0 aclkr0/clkx0/gp[99] aclkr0 clkx0 gp[99] afsr0/dr0/gp[100] afsr0 dr0 gp[100] ahclkr0/clkr0/gp[101] ahclkr0 clkr0 gp[101] spbk0 = 10 spbk0 = 01 spbk0 = 00 axr0[3]/fsr0/gp[102] axr0[3] fsr0 gp[102] axr0[2]/fsx0/gp[103] axr0[2] fsx0 gp[103] axr0[1]/dx0/gp[104] axr0[1] dx0 gp[104] serial port sub-block 1 axr0[0]/gp[105] axr0[0] spbk1 = 10 gp[105] aclkx0/gp[106] aclkx0 spbk1 = 10 gp[106] afsx0/gp[107] afsx0 spbk1 = 10 gp[107] ? ? spbk1 = 00 ahclkx0/gp[108] ahclkx0 spbk1 = 10 gp[108] amutein0/gp[109] amutein0 spbk1 = 10 gp[109] amute0/gp[110] amute0 spbk1 = 10 gp[110] as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, the mcbsp0 pins span across two pin mux blocks: serial port sub-block0, and timer0 block. for proper mcbsp0 operation, the serial port sub-block0 must be programmed to select mcbsp0 function. the mcbsp0 clks0 pin in the timer0 block is optional for mcbsp0 operation. clks0 is only needed if you desire using clks0 as an external clock source to the mcbsp0 internal sample rate generator. table 3-36 and table 3-37 provide a different view of the serial port block. table 3-36 shows the serial port sub-block 0 function based on pinmux1.spbk0 setting. table 3-37 shows the serial port sub-block 1 function based on pinmux1.spbk1 setting. these selection options are also shown pictorially in figure 3-11 . submit documentation feedback device configurations 117
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-36. serial port sub-block 0 function selection pinmux1.spbk0 block function resulting pin functions 00 gpio (6) ( default) gpio: gp[104:99] 01 mcbsp0 mcbsp0: clkx0, fsx0, dx0, clkr0, fsr0, dr0 mcasp0: aclkr0, afsr0, ahclkr0, axr0[3], 10 mcasp0 receive, 3 serializers axr0[2], axr0[1] 11 reserved reserved table 3-37. serial port sub-block 1 function selection pinmux1.spbk1 block function resulting pin functions 00 gpio (6) ( default) gpio: gp[110:105] 01 reserved reserved mcasp0 transmit with 1 serializer and mcasp0: axr0[0], aclkx0, afsx0, ahclkx0, 10 mute control amutein0 (1) , amute0 11 reserved reserved (1) the input from the amutein0/gp[109] pin is connected to both the mcasp0 and gpio. in addition, the vdd3p3v_pwdn.sp field determines the power state of the serial port block pins. the serial port block pins default to powered down and not operational. to use these pins, user must first program vdd3p3v_pwdn.sp = 0 to power up the pins. for more details on the vdd3p3v_pwdn.sp field, see section 3.2 , power considerations. to facilitate mcasp0 operation, the input from the amutein0/gp[109] pin is connected to both the mcasp0 and the gpio module. therefore when an external mute event occurs, in addition to notifying the mcasp0, it can also cause an interrupt through the gpio module. device configurations 118 submit documentation feedback
3.7.3.11 pwm1 block tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this block of 1 pin consists of pwm1 and gpio muxed pins (gp[4]/pwm1). the pinmux1.pwm1bk register field selects the pin function in the pwm1 block. table 3-38 summarizes the 1 pin in the pwm1 block, its multiplexed function, and the pinmux configurations to select the corresponding function. table 3-38. pwm1 block muxed pin selection multiplexed functions signal pwm1 gpio name function select function select gp[4]/pwm1 pwm1 pwm1bk = 1 gp[4] pwm1bk = 0 table 3-39 provides a different view of the pwm1 block pin muxing, showing the pwm1 block function based on pinmux1.pwm1bk setting. the selection options are also shown pictorially in figure 3-11 . table 3-39. pwm1 block function selection pinmux1.pwm1bk block function resulting pin functions 0 gpio (1) ( default) gpio: gp[4] 1 pwm1 pwm1: pwm1 in addition, the vdd3p3v_pwdn.pwm1 field determines the power state of the pwm1 block pin. the pwm1 block pin defaults to powered down and not operational. to use this pin, user must first program vdd3p3v_pwdn.pwm1 = 0 to power up the pin. for more details on the vdd3p3v_pwdn.pwm1 field, see section 3.2 , power considerations. submit documentation feedback device configurations 119
3.7.3.12 clkout block tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com this block of 1 pin consists of clkout, pwm2, and gpio muxed pin (clkout0/pwm2/gp[84]). the pinmux1.ckobk register field selects the pin function in the clkout block. table 3-40 summarizes the 1 pin in the clkout block, its multiplexed function, and the pinmux configurations to select the corresponding function. table 3-40. clkout block multiplexed pin selection multiplexed functions signal clkout0 pwm2 gpio name function select function select function select clkout0/ pwm2/ clkout0 ckobk = 01 pwm2 ckobk = 10 gp[84] ckobk = 00 gp[84] table 3-41 provides a different view of the clkout block pin muxing, showing the clkout block function based on pinmux1.ckobk setting. the selection options are also shown pictorially in figure 3-11 . table 3-41. clkout block function selection pinmux1.ckobk block function resulting pin functions 00 gpio (1) gpio: gp[84] 01 clkout ( default) device clock-out: clkout0 10 pwm2 pwm2: pwm2 11 reserved reserved this block defaults to clkout0 pin function. in addition, the vdd3p3v_pwdn.clkout field determines the power state of the clkout block pin. the clkout block pin defaults to powered up. for more details on the vdd3p3v_pwdn.clkout field, see section 3.2 , power considerations. device configurations 120 submit documentation feedback
3.7.3.13 emifa/vpss block muxing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 this block of 61 pins consists of vpss, emifa, pci, and gpio muxed pins. the following register fields affect the pin functions in the emifa/vpss block: all pinmux0 register fields: aem, vencsel, cs5sel, cs4sel, cs3sel, rgbsel, vpbecken, and aeaw pinmux1.pcien the emifa/vpss block is divided into multiple sub-blocks for ultimate flexibility in pin multiplexing to accommodate a wide variety of applications: sub-block 0: multiplexed between emifa data/address/control pins, pci, and gpio. sub-block 1: multiplexed between vpbe, emifa data/address/control pins, and gpio. sub-block 2: no multiplexing. emifa control pins em_wait/(rdy/ bsy), em_oe, em_we. sub-block 3: multiplexed between emifa address pins em_a[12:6], pci, and gpio. as discussed in section 3.7.3.2 , peripherals spanning multiple pin mux blocks, pci pins span across the following pin mux blocks: host block, emifa/vpss block sub-block 0 and sub-block 3, pci data block, and gpio block. for proper pci operation, pci must be selected in all of these pin mux blocks. the embk0, embk1, embk2, embk3 fields in the vdd3p3v_pwdn register determine the power state of the emifa/vpss block pins. the emifa/vpss block pins default to powered up. for more details on the embk0, embk1, embk2, embk3 fields in the vdd3p3v_pwdn register, see section 3.2 , power considerations. to understand pin multiplexing in the emifa/vpss block, the user should start with section 3.7.3.13.1 , emifa/vpss block pin selection procedure, which outlines the procedures to select pin functions of this block. section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary, provides a pin-by-pin multiplexing summary for the emifa/vpss block. for more information on the pinmux0 and pinmux1 registers, see section 3.7.2 , pin muxing selection after device reset. 3.7.3.13.1 emifa/vpss block pin selection procedure follow the steps below to perform pin selection for the emifa/vpss block and its sub-blocks. 1. major configuration options: start with table 3-42 , emifa/vpss block major configuration choices. based on the peripheral needs, the user should select from the major configuration options in this block: major config options a, b, c, d, e, f, g. 2. sub-block 0, sub-block 2, and sub-block 3 selection: after selecting the major configuration option from table 3-42 , emifa/vpss block major configuration choices, the pin selection for sub-block 0, sub-block 2, and sub-block 3 is complete. 3. sub-block 1 selection: use table 3-44 through table 3-48 , emifa/vpss sub-block 1 configuration choices, to refine sub-block 1 pin selection. a. go to the table with the major configuration option chosen in step 1. b. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. c. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields vencsel, rgbsel, cs3sel, cs4sel, and cs5sel. d. the selection fields columns shows the settings needed to program the pinmux0 register. after following the procedure in this section to determine pin functions for the emifa/vpss block, the user should refer to section 3.7.3.13.7 , emifa/vpss block pin-by-pin multiplexing summary, for pin-multiplexing information on a pin-by-pin basis. submit documentation feedback device configurations 121
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.13.2 emifa/vpss block major configuration choices table 3-42 shows the major configuration choices in the emifa/vpss block. for instructions on how to use the emifa/vpss block major configuration choices table for the emifa/vpss block and sub-blocks, see section 3.7.3.13.1 . table 3-42. emifa/vpss block major configuration choices pinmux selection fields (1) resulting peripherals/pins major config. vpbe and # gp pins # gp pins pcien aem vencsel pci (2) emifa option (from gp[33:5]) (from gp[54:34]) vencsel vpbe & # gp pins # gp pins no venc 00 29 gp pins 8-bit venc a 0 000 00, 01, 10 - - 01 21 gp pins 8-to-29-gp pins 16-to-24-bit venc 10 0-to-12 gp pins no venc 00 8-bit emifa (async) 9-to-13 gp pins b 0 001 (3) 00, 01 - pinout mode 1 with address 11 gp pins 8-bit venc (3) pins to support 16mb per cs. 01 (3) 0-to-4 gp pins no venc 8-bit emifa (async) 00 17-to-21 gp pins pinout mode 3 with address c 0 011 (3) 00, 10 - 12 gp pins pins to support up to 32kb 16-bit venc (3) 10 (3) per cs. 0-to-4 gp pins no venc 00 22-to-26 gp pins 8-bit emifa (nand) 8-bit venc d 0 100 00, 01, 10 - 01 13 gp pins pinout mode 4 12-to-17 gp pins 16-to-18-bit venc 10 2-to-9 gp pins no venc 00 14-to-18 gp pins 8-bit emifa (nand) e 0 101 00, 01 - 21 gp pins pinout mode 5 8- bit venc 01 4-to-9 gp pins no venc 00 29 gp pins 8-bit venc f 1 000 00, 01, 10 pci - 01 13 gp pins 8-to-29 gp pins 16-to-24-bit venc 10 0-to-12 gp pins no venc 00 14-to-18 gp pins 8-bit emifa (nand) g 1 101 00, 01 pci 13 gp pins pinout mode 5 8-bit venc 01 4-to-9 gp pins (1) for additional pin mux details for each sub-block, see table 3-44 through table 3-48 , emifa/vpss sub-block 1 configuration choices. (2) pci pins span across multiple pin mux blocks (section 3.7.3.2 , peripherals spanning multiple pin mux blocks). this table only refers to the pci pins in the emifa/vpss block. (3) if pinmux0.aem = 001 or 011, it is not possible to get lcd_field pin for vpbe. as shown in table 3-42 , the major configuration choices of the emifa/vpss block are determined by the following pinmux register fields: pinmux1 register field pcien pinmux0 register fields aem and vencsel based on the peripheral needs, select from the major configuration options in this block: major configuration options a, b, c, d, e, f, and g. 122 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the following is an example on how to read table 3-42 . for example, the "pinmux selection fields" columns indicate that major configuration choice b is selected through setting pinmux1.pcien = 0, pinmux0.aem = 1, and vencsel = 0 or 1 (based on the system's vpbe requirement). the "resulting peripherals/pins" columns indicate that major configuration option b can support the following combination of pin functions: no pci pins pins for 8-bit emifa (async or nand) function. the number of address pins supported provide 16mbyte address reach per emifa chip select (cs) space. pins for up to 8-bit vpbe. if 8-bit vpbe (vencsel = 1) is selected, the user may have 0 to 4 gpio pins. exact detail on number of gpio pins and vpbe control pins is further determined by other pinmux0 settings discussed in the emifa/vpss sub-block 1 configuration choices. 11 gpio pins (gp[54:52, 43:36]) from emifa/vpss sub-block 0. after using table 3-42 to select the major configuration option for the emifa/vpss block, proceed to select the detailed pin choices in the emifa/vpss sub-blocks. 3.7.3.13.3 emifa/vpss sub-block 0 configuration choices the pins in the emifa/vpss sub-block 0 are muxed between part of emifa, part of pci, and gpio. the pin functions in the emifa/vpss sub-block 0 are determined by the following pinmux register fields: pinmux1.pcien pinmux0:aem, aeaw ( must be set to 100b) once the major configuration option for the emifa/vpss block has been selected (see section 3.7.3.13.2 , emifa/vpss block major configuration choices), no further actions are necessary to refine the emifa/vpss sub-block 0 pin selection. for instructions on the procedures to configure the emifa/vpss block, see section 3.7.3.13.1 , emifa/vpss block pin selection procedure. table 3-43 summarizes the pin selections in the emifa/vpss sub-block 0 based on the pinmux selections. submit documentation feedback device configurations 123
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-43. emifa/vpss sub-block 0 configuration choices pinmux selection fields resulting peripherals/pins major config pcien aem aeaw pci emifa gpio option 21 gp pins: a 0 000 n/a ? ? gp[54:34] 8-bit emifa (async) pinout mode 1 11 gp pins: b 0 001 (1) 100 ? em_r/ w gp[54:52], gp[43:36] em_a[21:13] 8-bit emifa (async) 12 gp pins: pinout mode 3 c 0 011 n/a ? gp[54:52], gp[43:36], em_r/ w gp[34] em_d[7:0] 8-bit emifa (nand) 13 gp pins: d 0 100 n/a ? pinout mode 4 gp[54:52], gp[43:36], em_d[7:0] gp[35:34] 8-bit emifa (nand) pinout mode 5 21 gp pins: e 0 101 n/a ? no emifa pins from gp[54:34] sub-block 0 pci: 13 gp pins: preq, pinta, prst, f 1 000 n/a ? gp[54:52], gp[43:36], pgnt, ad31, ad29, gp[35:34] ad27, ad25 pci: 8-bit emifa (nand) 13 gp pins: preq, pinta, prst, pinout mode 5 g 1 101 n/a gp[54:52], gp[43:36], pgnt, ad31, ad29, no emifa pins from gp[35:34] ad27, ad25 sub-block 0 (1) for aem = 001, aeaw must be set to 100b. for aem = 000, 011, 100, or 101, aeaw is "don't care". 124 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 3.7.3.13.4 emifa/vpss sub-block 1 configuration choices table 3-44 through table 3-48 show the configuration choices in the emifa/vpss sub-block 1. for instructions on how to use the different configuration choices tables for the emifa/vpss block and sub-blocks, see section 3.7.3.13.1 , emifa/vpss block pin selection procedure. before using table 3-44 through table 3-48 to configure the details of the emifa/vpss sub-block 1, the user should first select the major configuration option for the emifa/vpss block (see section 3.7.3.13.2 , emifa/vpss block major configuration choices). after determining the major configuration option (a, b, c, d, e, f, or g), the user can now use table 3-44 through table 3-48 to refine the sub-block 1 pin selections. 1. go to the table with the major configuration option chosen from table 3-42 . 2. each major configuration option is further divided down into multiple minor configuration options. select a minor configuration option that best suits the application need. 3. within the chosen minor configuration option, further refine the detailed pin configurations by selecting the settings of pinmux0 fields vencsel, rgbsel, cs3sel, cs4sel, cs5sel, and vpbecken. 4. the pinmux selection fields columns give the user the settings needed to program the pinmux0 register. submit documentation feedback device configurations 125
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-44. emifa/vpss sub-block 1 configuration choices a and f (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa vpbe gpio option option cfg summary no emifa no venc 29 gp pins vencsel = 0 0 = gp[31, 29:14] rgbsel = 0 0 = gp[12:5] a1, f1 000 cs3sel = 0 0 = gp[13] - - cs4sel = 0 0 = gp[32] cs5sel = 0 0 = gp[33] vpbecken = 0 0 = gp[30] cfg summary no emifa 8-bit venc 8 to 29 gp pins 1 = vclk, vencsel = 1 1 = gp[21:14] yout[7:0] 0 = gp[12:5] 0 = none rgbsel = 0,1 1 = gp[12], 1 = lcd_field a2, f2 000 gp[10:5] - cs3sel = 0,2 2 = lcd_oe 0 = gp[13] cs4sel = 0,2 2 = vsync 0 = gp[32] a, f cs5sel = 0,2 2 = hsync 0 = gp[33] vpbecken = 0,1 1 = vpbeclk 0 = gp[30] cfg summary no emifa 16-to-24-bit venc 0 to 12 gp pins 2 = vclk, vencsel = 2 yout[7:0], - cout[7:0] 0 = none 0 = gp[12:5] 1 = lcd_field 1 = gp[12], 2 = r2, b2 gp[10:5] rgbsel = 0,1,2,3,4 3 = r2, b2, 2 = gp[12:7] a3, f3 000 lcd_field 3 = gp[12], - 4 = g0, b0, r0, g1, gp[10:7] b1, r1, r2, b2 4 = no gp cs3sel = 0,2 2 = lcd_oe 0 = gp[13] cs4sel = 0,2 2 = vsync 0 = gp[32] cs5sel = 0,2 2 = hsync 0 = gp[33] vpbecken = 0,1 1 = vpbeclk 0 = gp[30] (1) italics indicate mandatory settings for a given minor configuration option. 126 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-45. emifa/vpss sub-block 1 configuration choice b (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa vpbe gpio option option 8-bit emifa (async) cfg summary no venc 9-to-13 gp pins pinout mode 1 vencsel = 0 0 = em_d[7:0] - 0 = gp[31, 29:22] 0 = em_cs2, rgbsel = 0 em_a[4:0], - - em_ba[1:0] b1 001 cs3sel = 0,1 1 = em_cs3 - 0 = gp[13] cs4sel = 0,1 1 = em_cs4 - 0 = gp[32] cs5sel = 0,1 1 = em_cs5 - 0 = gp[33] 1 = vpbeclk, can vpbecken = 0,1 - 0 = gp[30] be used by dac b 8-bit emifa (async) cfg summary 8-bit venc 0-to-4 gp pins pinout mode 1 1 = vclk, vencsel = 1 1 = em_d[7:0] - yout[7:0] 0 = em_cs2, rgbsel = 0 em_a[4:0], - - b2 001 em_ba[1:0] cs3sel = 0,1,2 1 = em_cs3 2 = lcd_oe 0 = gp[13] cs4sel = 0,1,2 1 = em_cs4 2 = vsync 0 = gp[32] cs5sel = 0,1,2 1 = em_cs5 2 = hsync 0 = gp[33] vpbecken = 0,1 - 1 = vpbeclk 0 = gp[30] (1) italics indicate mandatory setting for a given minor configuration option. table 3-46. emifa/vpss sub-block 1 configuration choice c (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa vpbe gpio option option 8-bit emifa (async) cfg summary no venc 17-to-21 gp pins pinout mode 3 vencsel = 0 - - 0 = gp[31, 29:14] 0 = em_cs2, rgbsel = 0 em_a[4:0], - - em_ba[1:0] c1 011 cs3sel = 0,1 1 = em_cs3 - 0 = gp[13] cs4sel = 0,1 1 = em_cs4 - 0 = gp[32] cs5sel = 0,1 1 = em_cs5 - 0 = gp[33] 1 = vpbeclk, can vpbecken = 0,1 - 0 = gp[30] be used by dac c 8-bit emifa (async) cfg summary 16-bit venc 0-to-4 gp pins pinout mode 3 2 = vclk, vencsel = 2 - yout[7:0], - cout[7:0] 0 = em_cs2, c2 011 rgbsel = 0 em_a[4:0], - - em_ba[1:0] cs3sel = 0,1,2 1 = em_cs3 2 = lcd_oe 0 = gp[13] cs4sel = 0,1,2 1 = em_cs4 2 = vsync 0 = gp[32] cs5sel = 0,1,2 1 = em_cs5 2 = hsync 0 = gp[33] vpbecken = 0,1 - 1 = vpbeclk 0 = gp[30] (1) italics indicate mandatory setting for a given minor configuration option. submit documentation feedback device configurations 127
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-47. emifa/vpss sub-block 1 configuration choice d (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa vpbe gpio option option 8-bit emifa (nand) cfg summary no venc 22-to-26 gp pins pinout mode 4 vencsel = 0 - - 0 = gp[31, 29:14] 0 = em_a[2:1], rgbsel = 0 - 0 = gp[11:10, 7:5] em_cs2 d1 100 cs3sel = 0,1 1 = em_cs3 - 0 = gp[13] cs4sel = 0,1 1 = em_cs4 - 0 = gp[32] cs5sel = 0,1 1 = em_cs5 - 0 = gp[33] 1 = vpbeclk, vpbecken = 0,1 - can be used by 0 = gp[30] dac 8-bit emifa (nand) cfg summary 8-bit venc 12-to-17 gp pins pinout mode 4 1 = vclk, vencsel = 1 - 1 = gp[21:14] yout[7:0] 0 = em_a[2:1], em_cs2 0 = none 0 = gp[11:10, 7:5] rgbsel = 0,1 d2 100 1 = em_a[2:1], 1 = lcd_field 1 = gp[10, 7:5] em_cs2 cs3sel = 0,1,2 1 = em_cs3 2 = lcd_oe 0 = gp[13] d cs4sel = 0,1,2 1 = em_cs4 2 = vsync 0 = gp[32] cs5sel = 0,1,2 1 = em_cs5 2 = hsync 0 = gp[33] vpbecken = 0,1 - 1 = vpbeclk 0 = gp[30] 8-bit emifa (nand) 16-to-18-bit cfg summary 2-to-9 gp pins pinout mode 4 venc 2 = vclk, vencsel = 2 - yout[7:0], - cout[7:0] 0 = em_a[2:1], em_cs2 0 = none 1 = em_a[2:1], 0 = gp[11:10, 7:5] 1 = lcd_field em_cs2 1 = gp[10, 7:5] d3 100 rgbsel = 0,1,2,3 2 = r2, b2 2 = em_a[2:1], 2 = gp[11:10, 7] 3 = r2, b2, em_cs2 3 = gp[10, 7] lcd_field 3 = em_a[2:1], em_cs2 cs3sel = 0,1,2 1 = em_cs3 2 = lcd_oe 0 = gp[13] cs4sel = 0,1,2 1 = em_cs4 2 = vsync 0 = gp[32] cs5sel = 0,1,2 1 = em_cs5 2 = hsync 0 = gp[33] vpbecken = 0,1 - 1 = vpbeclk 0 = gp[30] (1) italics indicate mandatory setting for a given minor configuration option. 128 device configurations submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 3-48. emifa/vpss sub-block 1 configuration choices e and g (1) major minor pinmux selection fields resulting peripherals/pins config config aem others emifa vpbe gpio option option 8-bit emifa (nand) cfg summary no venc 14-to-18 gp pins pinout mode 5 vencsel = 0 0 = em_d[7:0] - 0 = gp[31, 29:22] 0 = em_a[2:1], rgbsel = 0 - 0 = gp[11:10, 7:5] em_cs2 e1,g1 101 cs3sel = 0,1 1 = em_cs3 - 0 = gp[13] cs4sel = 0,1 1 = em_cs4 - 0 = gp[32] cs5sel = 0,1 1 = em_cs5 - 0 = gp[33] 1 = vpbeclk, can vpbecken = 0,1 - 0 = gp[30] be used by dac 8-bit emifa (nand) e,g cfg summary 8-bit venc 4-to-9 gp pins pinout mode 5 1 = vclk, vencsel = 1 1 = em_d[7:0] - yout[7:0] 0 = em_a[2:1], em_cs2 0 = none 0 = gp[11:10, 7:5] rgbsel = 0,1 e2,g2 101 1 = em_a[2:1], 1 = lcd_field 1 = gp[10, 7:5] em_cs2 cs3sel = 0,1,2 1 = em_cs3 2 = lcd_oe 0 = gp[13] cs4sel = 0,1,2 1 = em_cs4 2 = vsync 0 = gp[32] cs5sel = 0,1,2 1 = em_cs5 2 = hsync 0 = gp[33] vpbecken = 0,1 - 1 = vpbeclk 0 = gp[30] (1) italics indicate mandatory setting for a given minor configuration option. as shown in table 3-44 through table 3-48 , the configuration choices of the emifa/vpss sub-block 1 are determined by the following pinmux register fields: pinmux0 register fields aem, vencsel, rgbsel, cs3sel, cs4sel, cs5sel, and vpbecken. the following is an example on how to read table 3-44 through table 3-48 using sub-block 1 minor configuration g2 as an example: the pinmux selection fields columns indicate that sub-block 1 minor configuration option g2 is selected through setting pinmux0 fields to aem = 5, vencsel = 1, rgbsel = 0 or 1 (based on whether the vpbe lcd_field pin is needed), cs3sel = 0/1/2 (based on the desired pin choice), cs4sel = 0/1/2 (based on the desired pin choice), cs5sel = 0/1/2 (based on the desired pin choice), and vpbecken = 0/1 (based on whether vpbe vpbeclk is needed). the resulting peripherals/pins columns show the functional pins resulting from the pinmux setting. for example, pinmux0.vencsel = 1 gives you the vclk and yout[7:0] pins for the vpbe, in addition to em_d[7:0] pins for the emifa. pinmux0.rgbsel = 1 gives you the lcd_field pin for the vpbe, along with em_a[2:1] and em_cs2 for the emifa, and 4 gp pins. submit documentation feedback device configurations 129
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com 3.7.3.13.5 emifa/vpss sub-block 2 configuration choices the 3 pins in the emifa/vpss sub-block 2 are standalone (non-multiplexed) pins. they always function as emifa control pins em_wait/(rdy/ bsy), em_oe, and em_we. no pin mux selection is necessary for this sub-block. 3.7.3.13.6 emifa/vpss sub-block 3 configuration choices the 8 pins in the emifa/vpss sub-block 3 are multiplexed between: emifa address pins em_a[12:5] pci pins: pcbe3, pidsel, ad[24:19] gpio pins gp[96:89] the pin functions in the emifa/vpss sub-block 3 are determined by the following pinmux register fields: pinmux1.pcien pinmux0.aem once the major configuration option for the emifa/vpss block (see section 3.7.3.13.2 , emifa/vpss block major configuration choices) is chosen, no further actions are necessary to refine the emifa/vpss sub-block 3 pin selection. for instructions on configuring the emifa/vpss block, see section 3.7.3.13.1 , emifa/vpss block pin selection procedure. table 3-49 summarizes the pin selections in the emifa/vpss sub-block 3 based on the pinmux selections. table 3-49. emifa/vpss sub-block 3 configuration choices major pinmux selection fields resulting peripherals/pins config pcien aem pci emifa gpio option a 0 000 - - gp[96:89] b 0 001 - em_a[12:5] - c 0 011 - em_a[12:5] - d 0 100 - - gp[96:89] e 0 101 - - gp[96:89] f 1 000 pcbe3, pidsel, ad[24:19] - - g 1 101 pcbe3, pidsel, ad[24:19] - - the following is an example on how to read table 3-49 using sub-block 3 major configuration c as an example: the pinmux selection fields columns indicate that sub-block 3 major configuration option c is selected through pinmux1.pcien = 0 and pinmux0.aem = 3. the resulting peripherals/pins columns show the functional pins resulting from the pinmux setting. in major configuration c, the user gets emifa address pins em_a[12:5] from sub-block 3. device configurations 130 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 3.7.3.13.7 emifa/vpss block pin-by-pin multiplexing summary this section summarizes the emifa/vpss block muxing on a pin-by-pin basis. it provides an alternative view to pin muxing in the emifa/vpss block. this section should only be used after following the procedures listed in section 3.7.3.13.1 to determine the actual emifa/vpss configuration option for the application need. table 3-50 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 0. these are the fields in the pinmux0 and pinmux1 registers that control the multiplexing in this sub-block: pinmux0: aem and aeaw pinmux1: pcien table 3-51 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 1. these are the fields in the pinmux0 register that control the multiplexing in this sub-block: pinmux0: aem, vencsel, rgbsel, cs5sel, cs4sel, cs3sel, vpbecken emifa/vpss sub-block 2 is dedicated to emifa pins em_wait/(rdy/ bsy), em_oe, and em_we. there is no pin multiplexing in this block. these pins always function as emifa control pins. table 3-52 shows the pin multiplexing control for each pin in the emifa/vpss sub-block 3. these are the fields in the pinmux0 and pinmux1 registers that control the multiplexing in this sub-block: pinmux0: aem pinmux1: pcien table 3-50. emifa/vpss sub-block 0 pin-by-pin mux control multiplexed functions emifa addr/ctrl emifa data signal name pci gpio (aem[2:0] = 1, 3) (aem[2:0] = 3, 4) function select function select function select function select gp[54] ? ? ? ? ? ? gp[54] ? gp[43] ? ? ? ? ? ? gp[43] gp[42] ? ? ? ? ? ? gp[42] gp[41] ? ? ? ? ? ? gp[41] gp[40] ? ? ? ? ? ? gp[40] gp[39] ? ? ? ? ? ? gp[39] gp[38] ? ? ? ? ? ? gp[38] gp[37] ? ? ? ? ? ? gp[37] gp[36] ? ? ? ? ? ? gp[36] gp[53] ? ? ? ? ? ? gp[53] ? gp[52] ? ? ? ? ? ? gp[52] em_a[13]/ad25/em_d[0]/gp[51] em_a[13] pcien = 0, em_d[0] pcien = 0, ad25 pcien = 1, gp[51] pcien = 0, aem = 1 (1) , aem = 3/4, aem = 0/5, aem = 0/5, em_a[14]/ad27/em_d[1]/gp[50] em_a[14] em_d[1] ad27 gp[50] aeaw = 4 aeaw = n/a (1) aeaw = n/a (1) aeaw = n/a (1) em_a[15]/ad29/em_d[2]/gp[49] em_a[15] pcien = 0, em_d[2] pcien = 0, ad29 pcien = 1, gp[49] pcien = 0, aem = 1 (1) , aem = 3/4, aem = 0/5, aem = 0/5, em_a[16]/ pgnt/em_d[3]/gp[48] em_a[16] em_d[3] pgnt gp[48] aeaw = 4 aeaw = n/a (1) aeaw = n/a (1) aeaw = n/a (1) em_a[17]/ad31/em_d[4]/gp[47] em_a[17] pcien = 0, em_d[4] pcien = 0, ad31 pcien = 1, gp[47] pcien = 0, aem = 1 (1) , aem = 3/4, aem = 0/5, aem = 0/5, em_a[18]/ prst/em_d[5]/gp[46] em_a[18] em_d[5] prst gp[46] aeaw = 4 aeaw = n/a (1) aeaw = n/a (1) aeaw = n/a (1) em_a[19]/ preq/em_d[6]/gp[45] em_a[19] pcien = 0, em_d[6] pcien = 0, preq pcien = 1, gp[45] pcien = 0, aem = 1 (1) , aem = 3/4, aem = 0/5, aem = 0/1/5, em_a[20]/ pinta/em_d[7]/gp[44] em_a[20] em_d[7] pinta gp[44] aeaw = 4 aeaw = n/a (1) aeaw = n/a (1) aeaw = n/a (1) em_r/ w/gp[35] em_r/ w aem = 1/3 ? ? ? ? gp[35] aem = 0/4/5 em_a[21]/gp[34] em_a[21] aem = 1 ? ? ? ? gp[34] aem = 0/3/4/5 (1) for aem = 1, aeaw[2:0] must be set to 100b. for aem = 0,3,4,5, the aeaw[2:0] setting is "don't care". submit documentation feedback device configurations 131
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 3-51. emifa/vpss sub-block 1 pin-by-pin mux control multiplexed functions signal vpbe vpbe emifa gpio name extra functions function select function select function select function select hsync/ em_cs5/gp[33] hsync cs5sel = 2 ? ? em_cs5 cs5sel = 1 gp[33] cs5sel = 0 vsync/ em_cs4/gp[32] vsync cs4sel = 2 ? ? em_cs4 cs4sel = 1 gp[32] cs4sel = 0 vpbeclk/gp[30] vpbeclk vpbecken = 1 ? ? ? ? gp[30] vpbecken = 0 vclk/gp[31] vclk vencsel = 1/2 ? ? ? ? gp[31] vencsel = 0 yout7/gp[29] yout7 ? ? ? ? gp[29] yout6/gp[28] yout6 ? ? ? ? gp[28] yout5/gp[27] yout5 ? ? ? ? gp[27] yout4/gp[26]/(fastboot) yout4 ? ? ? ? gp[26] yout3/gp[25]/(bootmode3) yout3 ? ? ? ? gp[25] yout2/gp[24]/(bootmode2) yout2 ? ? ? ? gp[24] yout1/gp[23]/(bootmode1) yout1 ? ? ? ? gp[23] yout0/gp[22]/(bootmode0) yout0 ? ? ? ? gp[22] cout7/em_d[7]/gp[21] cout7 vencsel = 2, ? ? em_d[7] vencsel = gp[21] vencsel = aem = 0/3/4 0/1, 0/1, cout6/em_d[6]/gp[20] cout6 ? ? em_d[6] gp[20] aem = 1/5 aem = 0/3/4 cout5/em_d[5]/gp[19] cout5 ? ? em_d[5] gp[19] cout4/em_d[4]/gp[18] cout4 ? ? em_d[4] gp[18] cout3/em_d[3]/gp[17] cout3 ? ? em_d[3] gp[17] cout2/em_d[2]/gp[16] cout2 ? ? em_d[2] gp[16] cout1/em_d[1]/gp[15] cout1 ? ? em_d[1] gp[15] cout0/em_d[0]/gp[14] cout0 ? ? em_d[0] gp[14] lcd_oe/ em_cs3/gp[13] lcd_oe cs3sel = 2 ? ? em_cs3 cs3sel = 1 gp[13] cs3sel = 0 g0/ em_cs2/gp[12] g0 ? ? em_cs2 gp[12] g1/em_a[1]/(ale)/ rgbsel = rgbsel = g1 ? ? em_a[1]/(ale) gp[9] gp[9]/(aeaw1/pllms1) 0/1 (1) , 0/1/2/3, aem = 1/3/4/5 aem = 0 b1/em_a[2]/(cle)/gp[8]/ b1 ? ? em_a[2]/(cle) gp[8] (aeaw0/pllms0) rgbsel = 4, lcd_field rgbsel = em_a[3] gp[11] rgbsel = aem = 0 b0/lcd_field/ b0 1/3 (1) , 0/2 (1) , em_a[3]/gp[11] aem = 0/4/5 aem = 0/4/5 r0/em_a[4]/gp[10]/ rgbsel = r0 ? ? em_a[4] gp[10] rgbsel = 0, (aeaw2/pllms2) 0/1/2/3 (1) , aem = 1/3 aem = 0/4/5 r1/em_a[0]/gp[7]/(aem2) r1 ? ? em_a[0] gp[7] r2/em_ba[0]/gp[6]/(aem1) r2 rgbsel = ? ? em_ba[0] gp[6] rgbsel = 0/1, 2/3/4, aem = 0/4/5 b2/em_ba[1]/gp[5]/(aem0) b2 ? ? em_ba[1] gp[5] aem = 0 (1) valid rgbsel settings depend on aem mode: rgbsel = 0 is valid for aem[2:0] = 0/1/3/4/5 rgbsel = 1 is only valid if aem[2:0] = 0/4/5 rgbsel = 2/3/4 is only valid if aem[2:0] = 0 table 3-52. emifa/vpss sub-block 3 pin-by-pin mux control multiplexed functions signal name emifa pci gpio function select function select function select em_a[12]/ pcbe3/gp[89] em_a[12] pcbe3 gp[89] em_a[11]/ad24/gp[90] em_a[11] ad24 gp[90] em_a[10]/ad23/gp[91] em_a[10] ad23 gp[91] em_a[9]/pidsel/gp[92] em_a[9] pidsel gp[92] pcien = 0, pcien = 1, pcien = 0, aem = 1/3 aem = 0/5 aem = 0/4/5 em_a[8]/ad21/gp[93] em_a[8] ad21 gp[93] em_a[7]/ad22/gp[94] em_a[7] ad22 gp[94] em_a[6]/ad20/gp[95] em_a[6] ad20 gp[95] em_a[5]/ad19/gp[96] em_a[5] ad19 gp[96] device configurations 132 submit documentation feedback
3.8 device initialization sequence after reset tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 software should follow this initialization sequence after coming out of device reset. 1. complete the boot sequence as needed. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). 2. if the device is not already at the desired operating frequency, program the pll controllers (pllc1 and pllc2) to configure the device frequency. for details on how to program the pllc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). 3. program pinmux0 and pinmux1 registers to select device pin functions. for more details on programming the pinmux0 and pinmux1 registers to select device pin functions, see section 3.7 , multiplexed pin configurations. note: if emac operation is desired, the emac must be placed in reset before programming pinmux1.hostbk to select emac pins. 4. program the vdd3p3v_pwdn register to power up the necessary i/o pins. for more details on programming the vdd3p3v_pwdn register, see section 3.2 , power considerations. 5. as needed by the application, program the following system module registers when there are no active transactions on the respective peripherals: a. hpictl (section 3.6.2.1 , hpi control register): applicable for hpi only if a different host burst write timeout value from default is desired. b. timerctl (section 3.6.2.2 , timer control register): applicable for timer0 and watchdog timer2 only. c. edmatccfg (section 3.6.2.3 , edma tc configuration register): applicable for edma only. the recommendation is to leave the edmatccfg register at its default. d. vpss_clkctl (section 3.3.1.2.1 , vpss clocks): applicable for vpss only. 6. program the power and sleep controller (psc) to enable the desired peripherals. for details on how to program the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). 7. program the switched central resource (scr) bus priorities for the master peripherals (section 3.6.1 ). this must be configured when there are no active transactions on the respective peripherals: a. program the mstpri0 and mstpri1 registers in the system module. these registers can be programmed before or after the respective peripheral is enabled by the psc in step 6. b. program the edmacc quepri register, the c64x+ mdmaarbe.pri field, and the vpss pcr register. these registers can only be programmed after the respective peripheral is enabled by the psc in step 6. 8. configure the c64x+ megamodule and the peripherals. a. for details on c64x+ megamodule configuration, see the tms320c64x+ dsp megamodule reference guide (literature number spru871 ). special considerations: bootloader disables c64x+ cache?for all boot modes that default to dspbootaddr = 0x0010 0000 (i.e., all boot modes except the emifa rom direct boot, bootmode[3:0] = 0100, fastboot = 0), the bootloader code disables all c64x+ cache (l2, l1p, and l1d) so that upon exit from the bootloader code, all c64x+ memories are configured as all ram (l2cfg.l2mode = 0h, l1pcfg.l1pmode = 0h, and l1dcfg.l1dmode = 0h). if cache use is required, the application code must explicitly enable the cache. for more information on boot modes, see section 3.4.1 , boot modes. for more information on the bootloader, see the using the tms320dm643x bootloader application report (literature number spraag0 ). submit documentation feedback device configurations 133
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com b. peripherals configuration: see the respective peripheral user?s guide. special considerations: ddr2 memory controller?the peripheral bus burst priority register (pbbpr) should be programmed to ensure good ddr2 throughput and to prevent command starvation (prevention of certain commands from being processed by the ddr2 memory controller). for more details, see the tms320dm643x dmp ddr2 memory controller user?s guide (literature number spru986 ). a hex value of 0x20 is recommended for the pbbpr pr_old_count field to provide a good dsp performance and still allow good utilization by other modules. 134 device configurations submit documentation feedback
3.9 debugging considerations 3.9.1 pullup/pulldown resistors tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 proper board design should ensure that input pins to the dm643x dmp device always be at a valid logic level and not floating. this may be achieved via pullup/pulldown resistors. the dm643x dmp features internal pullup (ipu) and internal pulldown (ipd) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors. an external pullup/pulldown resistor needs to be used in the following situations: boot and configuration pins: if the pin is both routed out and 3-stated (not driven), an external pullup/pulldown resistor is strongly recommended, even if the ipu/ipd matches the desired value/state. other input pins: if the ipu/ipd does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail. emifa chip select outputs: on dm6433, the emifa chip select pins ( em_cs2, em_cs3, em_cs4, and em_cs5) feature an internal pulldown (ipd) resistor. if these pins are connected and used as an emifa chip select signal, for proper device operation, an external pullup resistor must be used to ensure the em_csx function defaults to an inactive (high) state. for the boot and configuration pins (listed in table 2-5 , boot terminal functions), if they are both routed out and 3-stated (not driven), it is strongly recommended that an external pullup/pulldown resistor be implemented. although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device boot and configuration pins. in addition, applying external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in debugging and flexibility in switching operating modes. tips for choosing an external pullup/pulldown resistor: consider the total amount of current that may pass through the pullup or pulldown resistor. make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors. decide a target value for the net. for a pulldown resistor, this should be below the lowest v il level of all inputs connected to the net. for a pullup resistor, this should be above the highest v ih level of all inputs on the net. a reasonable choice would be to target the v ol or v oh levels for the logic family of the limiting device; which, by definition, have margin to the v il and v ih levels. select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. the current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net. for bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin). remember to include tolerances when selecting the resistor value. for pullup resistors, also remember to include tolerances on the dv dd rail. for most systems, a 1-k w resistor can be used to oppose the ipu/ipd while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for most systems, a 20-k w resistor can be used to compliment the ipu/ipd on the boot and configuration pins while meeting the above criteria. users should confirm this resistor value is correct for their specific application. for more detailed information on input current (i i ), and the low-/high-level input voltages (v il and v ih ) for the dm643x dmp, see section 5.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature. submit documentation feedback device configurations 135
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com for the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal functions table. 136 device configurations submit documentation feedback
4 system interconnect 4.1 system interconnect block diagram tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 on the dm6433 device, the c64x+ megamodule, the edma3 transfer controllers, and the system peripherals are interconnected through a switch fabric architecture (see figure 4-1 ). the switch fabric is composed of multiple switched central resources (scrs) and multiple bridges. the scrs establish low-latency connectivity between master peripherals and slave peripherals. additionally, the scrs provide priority-based arbitration and facilitate concurrent data movement between master and slave peripherals. through an scr, the dsp subsystem can send data to the ddr2 memory controller without affecting a data transfer between the emac and l2 memory. bridges are mainly used to perform bus-width conversion as well as bus operating frequency conversion. for example, in figure 4-1 , bridge 6 performs a frequency conversion between a bus operating at dsp/3 clock rate and a bus operating at dsp/6 clock rate. furthermore, bridge 5 performs a bus-width conversion between a 64-bit bus and a 32-bit bus. the c64x+ megamodule, the edma3 transfer controllers (edma3tc[2:0]), and the various system peripherals can be classified into two categories: master peripherals and slave peripherals. master peripherals are typically capable of initiating read and write transfers in the system and do not rely on the edma3 or on the cpu to perform transfers to and from them. the system master peripherals include the c64x+ megamodule, the edma3 transfer controllers, vlynq, emac, hpi, pci, and vpss. not all master peripherals may connect to all slave peripherals. the supported connections are designated by "y" in table 4-1 . table 4-1. system connection matrix slave peripherals/modules master ddr2 c64x+ pci scr2, scr6, peripherals/modules memory scr4 (1) sdma (master back-end i/f) scr7, scr8 (1) controller c64x+ mdma ? y y ? y vpss ? y ? ? ? pci (slave back-end i/f) y y ? y y vlynq y y ? y y emac y y ? y y hpi y y ? y y edma3tc's y y y y y (edma3tc2/tc1/tc0) c64x+ cfg ? ? ? y y (1) all the peripherals/modules that support a connection to scr2, scr4, scr6, scr7, and scr8 have access to all peripherals/modules connected to those respective scrs. figure 4-1 displays the dm6433 system interconnect block diagram. the following is a list that helps in the interpretation of this diagram: the direction of the arrows indicates either a bus master or bus slave. the arrow originates at a bus master and terminates at a bus slave. the direction of the arrows does not indicate the direction of data flow. data flow is typically bi-directional for each of the documented bus paths. the pattern of each arrow's line indicates the clock rate at which it is operating? i.e., either dsp/3, dsp/6, or mxi/clkin clock rate. a peripheral may have multiple instances shown in figure 4-1 for the following reason: ? the peripheral/module has master port(s) for data transfers, as well as slave port(s) for register access, data access, and/or memory access. examples of these peripherals are c64x+ megamodule, edma3, vpss, vlynq, hpi, emac, and pci. submit documentation feedback system interconnect 137
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 4-1. system interconnect block diagram system interconnect 138 submit documentation feedback emac control module reg emac control module ram bridge 8 scr 3 scr 1 vlynq emac hpi vpss edma3tc0 edma3tc1 scr 5 bridge 2 l2 cache edma3tc0 edma3tc1 read write 6464 64 64 32 32 32 edma3cc edma3tc2 32 bridge 1 bridge 7 64 pci (dsp master i/f) 32 bridge 5 64 bridge 4 64 bridge 3 64 3232 scr 4 bridge 6 32 pci reg 32 32 32 32 32 32 edma3tc2 scr 6 hpi vpss reg emac reg mdio gpio system reg psc pllc1 pllc2 scr 2 uart0 i2c pwm0 pwm1 pwm2 timer0 timer1 timer2 scr 7 emifa vlynq scr 8 dsp/3 clock ratedsp/6 clock rate mxi/clkin clock rate 64x+ l2/l1 sdma ddr2 memory controller (memory/register) pci (dsp slave i/f) read write 6464 read write 64 64 64 64 64x+ mdma cfg 64 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 3232 32 32 32 32 32 32 32 32 64 dsp/6 clock rate dsp/3 clock rate dsp/6 clock rate mxi/clkin clock rate mcbsp0 mcasp0 32 32
5 device operating conditions 5.1 absolute maximum ratings over operating temperature range (unless otherwise tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 noted) (1) supply voltage ranges: core (cv dd , v dda_1p1v (2) ) (3) ?0.5 v to 1.5 v i/o, 3.3v (dv dd33 ) (3) ?0.5 v to 4.2 v i/o, 1.8v (dv ddr2 , ddr_vdddll, pll pwr18 , v dda_1p8v , mxv dd ) (3) ?0.5 to 2.5 v input voltage ranges: v i i/o, 3.3-v pins (except pci-capable pins) ?0.5 v to 4.2 v v i i/o, 3.3-v pins pci-capable pins ?0.5 v to dv dd33 + 0.5 v v i i/o, 1.8 v ?0.5 v to 2.5 v output voltage ranges: v o i/o, 3.3-v pins (except pci-capable pins) ?0.5 v to 4.2 v v o i/o, 3.3-v pins pci-capable pins ?0.5 v to dv dd33 + 0.5 v v o i/o, 1.8 v ?0.5 v to 2.5 v operating junction temperature commercial 0 c to 90 c ranges, t j : automotive (q or s suffix) ?40 c to 125 c storage temperature range, t stg (default) ?65 c to 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) based on jesd22-c101c ( field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components) testing the tms320dm643xzdu device?s charged-device model (cdm) sensitivity classification is class ii (200 to < 500 v) when subjected to the required 3 discharges. when subjected to one discharge (+ and -), the classification is class iii which is the standard texas instruments' cdm design goal. all pins except the vdda_1p1v (t20) pin associated with the dac module demonstrate class iii performance. (3) all voltage values are with respect to v ss. submit documentation feedback device operating conditions 139
5.2 recommended operating conditions (1) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com min nom max unit (-7/-6/-5/-4/-l/-q6/-q5/-q4 1.14 1.2 1.26 v supply voltage, core (cv dd , devices) cv dd v dda_1p1v ) (2) (-7/-6/-5/-4/-l/-q5 devices) 1.0 1.05 1.1 v supply voltage, i/o, 3.3v (dv dd33 ) 2.97 3.3 3.63 v dv dd supply voltage, i/o, 1.8v (dv ddr2 , ddr_vdddll, pll pwr18 , v dda_1p8v , 1.71 1.8 1.89 v mxv dd (3) ) v ss supply ground (v ss , v ssa_1p8v , v ssa_1p1v , ddr_vssdll, mxv ss (4) ) 0 0 0 v ddr_vref ddr2 reference voltage (5) 0.49dv ddr2 0.5dv ddr2 0.51dv ddr2 v ddr_zp ddr2 impedance control, connected via 200 w resistor to v ss v ss v ddr_zn ddr2 impedance control, connected via 200 w resistor to dv ddr2 dv ddr2 v dac_vref dac reference voltage input 0.475 0.5 0.525 v dac_rbias dac biasing, connected via 4 k w resistor to v ssa_1p8v v ssa_1p8v v high-level input voltage, 3.3v (except pci-capable and i2c pins) 2 v high-level input voltage, mxi/ clkin 0.65mxv dd v v ih high-level input voltage, pci 0.5dv dd33 dv dd33 + 0.5 v high-level input voltage, i2c 0.7dv dd33 v low-level input voltage, 3.3v (except pci-capable and i2c pins) 0.8 v low-level input voltage, mxi/ clkin 0.35mxv dd v v il low-level input voltage, pci ?0.5 0.3dv dd33 v low-level input voltage, i2c 0 0.3dv dd33 v commercial 0 90 c t j operating junction temperature (6) (7) automotive (q or s suffix) ?40 125 c commercial 0 70 c t a operating ambient temperature (7) automotive (q or s suffix) -40 85 c -7 devices 700 mhz -q6 devices 660 mhz dsp operating frequency (sysclk1), -6/ -l devices 600 mhz cv dd = 1.2 v -5/-q5 devices 500 mhz f sysclk1 (2) -4/-q4 devices 400 mhz -7 devices 560 mhz dsp operating frequency -6/-l devices 450 mhz (sysclk1), -5/-q5 devices 400 mhz cv dd = 1.05 v -4 devices 350 mhz (1) the actual voltage must be determined at device power-up, and not be changed dynamically during run-time. (2) applies to "tape and reel" part number counterparts as well. for more information, see section 2.8 , device and development-support tool nomenclature. (3) oscillator 1.8 v power supply (mxv dd ) can be connected to the same 1.8 v power supply as dv ddr2 . (4) oscillator ground (mxv ss ) must be kept separate from other grounds and connected directly to the crystal load capacitor ground. (5) ddr_vref is expected to equal 0.5dv ddr2 of the transmitting device and to track variations in the dv ddr2 . (6) in the absence of a heat sink or direct thermal attachment on the top of the device, use the following formula to determine the device junction temperature: t j = t c + (power x psi jt ). power and t c can be measured by the user. section 7.1 , thermal data for zwt and section 7.1.1 , thermal data for zdu provide the junction-to-package top (psi jt ) value based on airflow in the system. in the presence of a heat sink or direct thermal attachment on the top of the device, additional calculations and considerations must be taken into account. for more detailed information on thermal considerations, measurements, and calculations, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). (7) applications must meet both the operating junction temperature and operating ambient temperature requirements. for more detailed information on thermal considerations, measurements, and calculations, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). device operating conditions 140 submit documentation feedback
5.3 electrical characteristics over recommended ranges of supply voltage and operating tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 temperature (unless otherwise noted) parameter test conditions (1) min typ max unit high-level output voltage (3.3v i/o except dv dd33 = min, i oh = max 2.4 v pci-capable and i2c pins) v oh high-level output voltage (3.3v i/o i oh = -0.5 ma, dv dd33 = 3.3 v 0.9dv dd33 (2) v pci-capable pins) low-level output voltage (3.3v i/o except dv dd33 = min, i ol = max 0.4 v pci-capable and i2c pins) v ol low-level output voltage (3.3v i/o i oh = 1.5 ma, dv dd33 = 3.3 v 0.1dv dd33 (2) v pci-capable pins) low-level output voltage (3.3v i/o i2c pins) i o = 3 ma 0 0.4 v v i = v ss to dv dd33 with internal pullup resistor 50 100 250 m a (4) input current [dc] (except i2c and pci capable pins) v i = v ss to dv dd33 with internal pulldown ?250 ?100 ?50 m a resistor (4) input current [dc] (i2c) v i = v ss to dv dd33 10 m a i i (3) 0 < v i < dv dd33 = 3.3 v without internal resistor 50 m a 0 < v i < dv dd33 = 3.3 v with internal pullup 50 250 m a input current (pci capable pins) [dc] (5) resistor (4) 0 < v i < dv dd33 = 3.3 v with internal pulldown ?250 ?50 m a resistor (4) clk_out0/pwm2/gpio[84] and -8 ma vlynq_clock/pciclk/gp[57] ddr2 ?13.4 ma i oh high-level output current [dc] pci-capable pins ?0.5 (2) ma all other peripherals -4 ma clk_out0/pwm2/gpio[84] and 8 ma vlynq_clock/pciclk/gp[57] ddr2 13.4 ma i ol low-level output current [dc] pci-capable pins 1.5 (2) ma all other peripherals 4 ma v o = dv dd33 or v ss ; internal pull disabled 50 m a i oz (6) i/o off-state output current v o = dv dd33 or v ss ; internal pull enabled 100 m a cv dd = 1.2 v, dsp clock = 700 mhz 597 ma cv dd = 1.2 v, dsp clock = 660 mhz 560 ma cv dd = 1.2 v, dsp clock = 600 mhz 524 ma cv dd = 1.2 v, dsp clock = 500 mhz 460 ma i cdd core (cv dd , v dda_1p1v ) supply current (7) cv dd = 1.2 v, dsp clock = 400 mhz 392 ma cv dd = 1.05 v, dsp clock = 560 mhz 442 ma cv dd = 1.05 v, dsp clock = 450 mhz 372 ma cv dd = 1.05 v, dsp clock = 400 mhz 341 ma (1) for test conditions shown as min, max, or nom, use the appropriate value specified in the recommended operating conditions table. (2) these rated numbers are from the pci local bus specification revision 2.3. the dc specifications and ac specifications are defined in table 4-3 (dc specifications for 3.3v signaling) and table 4-4 (ac specifications for 3.3v signaling), respectively. (3) i i applies to input-only pins and bi-directional pins. for input-only pins, i i indicates the input leakage current. for bi-directional pins, i i indicates the input leakage current and off-state (hi-z) output leakage current. (4) applies only to pins with an internal pullup (ipu) or pulldown (ipd) resistor. (5) pci input leakage currents include hi-z output leakage for all bidirectional buffers with 3-state outputs. (6) i oz applies to output-only pins, indicating off-state (hi-z) output leakage current. (7) measured under the following conditions: 60% dsp cpu utilization doing typical activity (peripheral configurations, other housekeeping activities); ddr2 memory controller at 50% utilization (135 mhz), 50% writes, 32 bits, 50% bit switching; 2 mhz mcbsp0 at 100% utilization and 50% switching; timer0 at 100% utilization. at room temperature (25 c) for typical process zwt devices. the actual current draw varies across manufacturing processes and is highly application-dependent. dm643x dmp devices are offered in two basic options: lower-power option and high-performance option. low-power devices offer lower power consumption across temperature and voltage when compared with high-performance devices. however, high-performance devices offer higher operating speeds. for more details on core and i/o activity, high-performance and low-power device power consumption, as well as information relevant to board power supply design, see the tms320dm643x power consumption summary application report (literature number spraao6 ). submit documentation feedback device operating conditions 141
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com electrical characteristics over recommended ranges of supply voltage and operating temperature (unless otherwise noted) (continued) parameter test conditions (1) min typ max unit dv dd = 3.3 v, cv dd = 1.2 v, dsp clock = 700 13 ma mhz dv dd = 3.3 v, cv dd = 1.2 v, dsp clock = 660 13 ma mhz dv dd = 3.3 v, cv dd = 1.2 v, dsp clock = 600 13 ma mhz dv dd = 3.3 v, cv dd = 1.2 v, dsp clock = 500 13 ma mhz i ddd 3.3v i/o (dv dd33 ) supply current (7) dv dd = 3.3 v, cv dd = 1.2 v, dsp clock = 400 13 ma mhz dv dd = 3.3 v, cv dd = 1.05 v, dsp clock = 560 13 ma mhz dv dd = 3.3 v, cv dd = 1.05 v, dsp clock = 450 13 ma mhz dv dd = 3.3 v, cv dd = 1.05 v, dsp clock = 400 13 ma mhz dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 700 94 ma mhz dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 660 94 ma mhz dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 600 93 ma mhz dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 500 92 ma mhz 1.8v i/o (dv ddr2 , ddr_vdddll, pllv prw18 , i ddd v dda_1p8v , mxv dd ) supply current (7) dv dd = 1.8 v, cv dd = 1.2 v, dsp clock = 400 91 ma mhz dv dd = 1.8 v, cv dd = 1.05 v, dsp clock = 560 74 ma mhz dv dd = 1.8 v, cv dd = 1.05 v, dsp clock = 450 73 ma mhz dv dd = 1.8 v, cv dd = 1.05 v, dsp clock = 400 72 ma mhz c i input capacitance 5 pf c o output capacitance 5 pf 142 device operating conditions submit documentation feedback
6 peripheral information and electrical specifications 6.1 parameter information 6.1.1 3.3-v signal transition levels 6.1.2 3.3-v signal transition rates 6.1.3 timing parameters and board routing analysis tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-1. test load circuit for ac timing measurements the load capacitance value stated is only for characterization and measurement of ac timing signals. this load capacitance value does not indicate the maximum load the device is capable of driving. all input and output timing parameters are referenced to v ref for both "0" and "1" logic levels. for 3.3 v i/o, v ref = 1.5 v. for 1.8 v i/o, v ref = 0.9 v. figure 6-2. input and output voltage reference levels for ac timing measurements all rise and fall transition timing parameters are referenced to v il max and v ih min for input clocks, v ol max and v oh min for output clocks. figure 6-3. rise and fall transition time voltage reference levels all timings are tested with an input edge rate of 4 volts per nanosecond (4 v/ns). the timing parameter values specified in this data sheet do not include delays by board routings. as a good board design practice, such delays must always be taken into account. timing values may be adjusted by increasing/decreasing such delays. submit documentation feedback peripheral information and electrical specifications 143 t ransmission line 4.0 pf 1.85 pf z0 = 50 w (see note) tester pin electronics data sheet t iming reference point outputunder test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmission line ef fects must be taken into account. a transmission line with a delay of 2 ns can be used to produce the desired transmission line ef fect. the transmission line is intended as a load only . it is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. input requirements in this data sheet are tested with an input slew rate of < 4 v olts per nanosecond (4 v/ns) at the device pin. 42 w 3.5 nh device pin(see note) v ref v ref = v il max (or v ol max) v ref = v ih min (or v oh min)
6.2 recommended clock and control signal transition behavior 6.3 power supplies 6.3.1 power-supply sequencing 6.3.2 power-supply design considerations 6.3.3 power-supply decoupling tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com ti recommends utilizing the available i/o buffer information specification (ibis) models to analyze the timing characteristics correctly. to properly use ibis models to attain accurate timing analysis for a given system, see the using ibis models for timing analysis application report (literature number spra839 ). if needed, external logic hardware such as buffers may be used to compensate any timing differences. for the ddr2 memory controller interface, it is not necessary to use the ibis models to analyze timing characteristics. ti provides a pcb routing rules solution that describes the routing rules to ensure the ddr2 memory controller interface timings are met. see the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). all clocks and control signals must transition between v ih and v il (or between v il and v ih ) in a monotonic manner. for more information regarding ti's power management products and suggested devices to power ti dsps, visit www.ti.com/dsppower . the dm6433 includes one core supply (cv dd ), and two i/o supplies?dv dd33 and dv ddr2 . to ensure proper device operation, a specific power-up sequence must be followed. some ti power-supply devices include features that facilitate power sequencing?for example, auto-track and slow-start/enable features. for more information on ti power supplies and their features, visit www.ti.com/dsppower . here is a summary of the power sequencing requirements: the power ramp order must be dv dd33 before dv ddr2 , and dv ddr2 before cv dd ?meaning during power up, the voltage at the dv ddr2 rail should never exceed the voltage at the dv dd33 rail. similarly, the voltage at the cv dd rail should never exceed the voltage at the dv ddr2 rail. from the time that power ramp begins, all power supplies (dv dd33 , dv ddr2 , cv dd ) must be stable within 200 ms. the term "stable" means reaching the recommended operating condition (see section 5.2 , recommended operating conditions table). core and i/o supply voltage regulators should be located close to the dsp to minimize inductance and resistance in the power delivery path. additionally, when designing for high-performance applications utilizing the dm6433 device, the pc board should include separate power planes for core, i/o, and ground; all bypassed with high-quality low-esl/esr capacitors. in order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the dsp. these caps need to be close to the dsp, no more than 1.25 cm maximum distance to be effective. physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. larger caps for each supply can be placed further away for bulk decoupling. large bulk caps (on the order of 100 m f) should be furthest away, but still as close as possible. large caps for each supply should be placed outside of the bga footprint. as with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. for more details on capacitor usage and placement, see the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). peripheral information and electrical specifications 144 submit documentation feedback
6.3.4 dm6433 power and clock domains tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the dm6433 includes one single power domain ? the "always on" power domain. the "always on" power domain is always on when the chip is on. the "always on" domain is powered by the cv dd pins of the dm6433. all dm6433 modules lie within the "always on" power domain. table 6-1 provides a listing of the dm6433 clock domains. one primary reference clock is required for the dm6433 device. it can be either a crystal input or driven by external oscillators. a 27-mhz crystal is recommended for the plls, which generate the internal clocks for the digital media processor (dmp), peripherals, and edma3. the dm6433 architecture is divided into the power and clock domains shown in table 6-1 . table 6-2 and table 6-3 further discuss the clock domains and their ratios. figure 6-4 shows the clock domain block diagram. table 6-1. dm6433 power and clock domains power domain clock domain peripheral/module always on clkin uart0 always on clkin i2c always on clkin timer0 always on clkin timer1 always on clkin timer2 always on clkin pwm0 always on clkin pwm1 always on clkin pwm2 always on clkdiv3 ddr2 always on clkdiv3 vpss always on clkdiv3 edma always on clkdiv3 pci always on clkdiv3 scr always on clkdiv6 gpsc always on clkdiv6 lpscs always on clkdiv6 pllc1 always on clkdiv6 pllc2 always on clkdiv6 ice pick always on clkdiv6 emifa always on clkdiv6 hpi always on clkdiv6 vlynq always on clkdiv6 emac always on clkdiv6 mcasp0 always on clkdiv6 mcbsp0 always on clkdiv6 gpio always on clkdiv1 c64x+ cpu submit documentation feedback peripheral information and electrical specifications 145
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-2. dm6433 clock domains domain clock fixed ratio vs. example subsystem clock domain source sysclk1 frequency frequency (mhz) peripherals (clkin domain) clkin pllc1 auxclk (1) ? 27 mhz dsp subsystem clkdiv1 pllc1 sysclk1 1:1 594 mhz edma3 clkdiv3 pllc1 sysclk2 1:3 198 mhz vpss clkdiv3 pllc1 sysclk2 1:3 198 mhz peripherals (clkdiv3 domain) clkdiv3 pllc1 sysclk2 1:3 198 mhz peripherals (clkdiv6 domain) clkdiv6 pllc1 sysclk3 1:6 99 mhz (1) pllc1 auxclk runs at exactly the same frequency as the device clock source from the mxi/clkin pin. the clkdiv1:clkdiv3:clkdiv6 ratio must be strictly followed by programming the pll controller 1 (pllc1) plldiv1, plldiv2, and plldiv3 registers appropriately (see table 6-3 ). table 6-3. pllc1 programming for clkdiv1, clkdiv3, clkdiv6 domains clkdiv1 domain clkdiv3 domain clkdiv6 domain (sysclk1) (sysclk2) (sysclk3) pll1 pll1 pll1 plldiv1.ratio plldiv2.ratio plldiv3.ratio divide-down divide-down divide-down div1 /1 0 /3 2 /6 5 div2 /2 1 /6 5 /12 11 div3 /3 2 /9 8 /18 17 peripheral information and electrical specifications 146 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-4. pll1 and pll2 clock domain block diagram for further detail on pll1 and pll2, see the structure block diagrams figure 6-5 and figure 6-6 , respectively. submit documentation feedback peripheral information and electrical specifications 147 dsp subsystem sysclk1 sysclk3 scr edma vpfe resizer vpbe dacs ddr2 phy ddr2 vtp ddr2 mem ctlr plldiv2 (/10) plldiv1 (/2) bpdiv pll controller 2 pll controller 1 plldiv2 (/3) plldiv3 (/6) plldiv1 (/1) sysclk2 uart0 i2c t imers (x3) pwms (x3) emac emifa vlynq hpi mcasp0 mcbsp0 gpio pci mxi/clkin (27 mhz) vpbeclk oscdiv1 (/1) obsclk(clkout0 pin) bpdiv (/1) sysclkbp auxclk
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 6-5. pll1 structure block diagram figure 6-6. pll2 structure block diagram 148 peripheral information and electrical specifications submit documentation feedback plldiv1 (/1) plldiv3 (/6) plldiv2 (/3) sysclk1(clkdiv1 domain) sysclk3(clkdiv6 domain) sysclk2(clkdiv3 domain) 10 pllm pll 0 1 bpdiv clkmode clkin oscin pllen sysclkbp(vpss-vpbe clock source) obsclk(clkout0 pin) pllout auxclk(clkin domain) oscdiv1 plldiv2 (/10) plldiv1 (/2) 10 pllm pll 0 1 bpdiv clkmode clkin oscin pllen pll2_sysclk2(vpss?vpbe) pll2_sysclk1 (ddr2 phy) pll2_sysclkbp (ddr2 vtp) pllout
6.3.5 power and sleep controller (psc) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the power and sleep controller (psc) controls power by turning off unused power domains or by gating off clocks to individual peripherals/modules. the dm6433 device only utilizes the clock gating feature of the psc for power savings. the psc consists of a global psc (gpsc) and a set of local pscs (lpscs). the gpsc contains memory mapped registers, psc interrupt control, and a state machine for each peripheral/module. an lpsc is associated with each peripheral/module and provides clock and reset control. the lpscs for dm6433 are shown in table 6-4 . the psc register memory map is given in table 6-5 . for more details on the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). submit documentation feedback peripheral information and electrical specifications 149
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-4. dm6433 lpsc assignments lpsc peripheral/module lpsc peripheral/module lpsc peripheral/module number number number 0 vpss dma 14 emifa 28 timer1 1 vpss mmr 15 pci 29 reserved 2 edmacc 16 mcbsp0 30 reserved 3 edmatc0 17 reserved 31 reserved 4 edmatc1 18 i2c 32 reserved 5 edmatc2 19 uart0 33 reserved 6 emac memory controller 20 reserved 34 reserved 7 mdio 21 reserved 35 reserved 8 emac 22 reserved 36 reserved 9 mcasp0 23 pwm0 37 reserved 10 reserved 24 pwm1 38 reserved 11 vlynq 25 pwm2 39 c64x+ cpu 12 hpi 26 gpio 40 reserved 13 ddr2 memory controller 27 timer0 table 6-5. psc register memory map register hex address range description acronym 0x01c4 1000 pid peripheral revision and class information register 0x01c4 1004 - 0x01c4 100f ? reserved 0x01c4 1010 gblctl global control register 0x01c4 1014 ? reserved 0x01c4 1018 inteval interrupt evaluation register 0x01c4 101c - 0x01c4 103f ? reserved 0x01c4 1040 merrpr0 module error pending 0 (mod 0 - 31) register 0x01c4 1044 merrpr1 module error pending 1 (mod 32- 63) register 0x01c4 1048 - 0x01c4 104f ? reserved 0x01c4 1050 merrcr0 module error clear 0 (mod 0 - 31) register 0x01c4 1054 merrcr1 module error clear 1 (mod 32 - 63) register 0x01c4 1058 - 0x01c4 105f ? reserved 0x01c4 1060 perrpr power error pending register 0x01c4 1064 - 0x01c4 1067 ? reserved 0x01c4 1068 perrcr power error clear register 0x01c4 106c - 0x01c4 111f ? reserved 0x01c4 1120 ptcmd power domain transition command register 0x01c4 1124 - 0x01c4 1127 ? reserved 0x01c4 1128 ptstat power domain transition status register 0x01c4 112c - 0x01c4 11ff ? reserved 0x01c4 1200 pdstat0 power domain status 0 register (always on) 0x01c4 1204 - 0x01c4 12ff ? reserved 0x01c4 1300 pdctl0 power domain control 0 register (always on) 0x01c4 1304 - 0x1c4 150f ? reserved 0x01c4 1510 mckout0 module clock output status (mod 0-31) register 0x01c4 1514 mckout1 module clock output status (mod 32-63) register 0x01c4 1518 - 0x01c4 15ff ? reserved 0x01c4 1600 - 0x01c4 17ff ? reserved peripheral information and electrical specifications 150 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-5. psc register memory map (continued) register hex address range description acronym 0x01c4 1800 mdstat0 module status 0 register (vpss dma) 0x01c4 1804 mdstat1 module status 1 register (vpss mmr) 0x01c4 1808 mdstat2 module status 2 register (edmacc) 0x01c4 180c mdstat3 module status 3 register (edmatc0) 0x01c4 1810 mdstat4 module status 4 register (edmatc1) 0x01c4 1814 mdstat5 module status 5 register (emactc2) 0x01c4 1818 mdstat6 module status 6 register (emac memory controller) 0x01c4 181c mdstat7 module status 7 register (mdio) 0x01c4 1820 mdstat8 module status 8 register (emac) 0x01c4 1824 mdstat9 module status 9 register (mcasp0) 0x01c4 1828 ? reserved 0x01c4 182c mdstat11 module status 11 register (vlynq) 0x01c4 1830 mdstat12 module status 12 register (hpi) 0x01c4 1834 mdstat13 module status 13 register (ddr2) 0x01c4 1838 mdstat14 module status 14 register (emifa) 0x01c4 183c mdstat15 module status 15 register (pci) 0x01c4 1840 mdstat16 module status 16 register (mcbsp0) 0x01c4 1844 ? reserved 0x01c4 1848 mdstat18 module status 18 register (i2c) 0x01c4 184c mdstat19 module status 19 register (uart0) 0x01c4 1850 ? reserved 0x01c4 1854 ? reserved 0x01c4 1858 ? reserved 0x01c4 185c mdstat23 module status 23 register (pwm0) 0x01c4 1860 mdstat24 module status 24 register (pwm1) 0x01c4 1864 mdstat25 module status 25 register (pwm2) 0x01c4 1868 mdstat26 module status 26 register (gpio) 0x01c4 186c mdstat27 module status 27 register (timer0) 0x01c4 1870 mdstat28 module status 28 register (timer1) 0x01c4 1874 - 0x01c4 189b ? reserved 0x01c4 189c mdstat39 module status 39 register (c64x+ cpu) 0x01c4 18a0 ? 0x01c4 18a4 - 0x01c4 19ff ? reserved 0x01c4 1a00 mdctl0 module control 0 register (vpss dma) 0x01c4 1a04 mdctl1 module control 1 register (vpss mmr) 0x01c4 1a08 mdctl2 module control 2 register (edmacc) 0x01c4 1a0c mdctl3 module control 3 register (edmatc0) 0x01c4 1a10 mdctl4 module control 4 register (edmatc1) 0x01c4 1a14 mdctl5 module control 5 register (emactc2) 0x01c4 1a18 mdctl6 module control 6 register (emac memory controller) 0x01c4 1a1c mdctl7 module control 7 register (mdio) 0x01c4 1a20 mdctl8 module control 8 register (emac) 0x01c4 1a24 mdctl9 module control 9 register (mcasp0) 0x01c4 1a28 ? reserved 0x01c4 1a2c mdctl11 module control 11 register (vlynq) 0x01c4 1a30 mdctl12 module control 12 register (hpi) submit documentation feedback peripheral information and electrical specifications 151
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-5. psc register memory map (continued) register hex address range description acronym 0x01c4 1a34 mdctl13 module control 13 register (ddr2) 0x01c4 1a38 mdctl14 module control 14 register (emifa) 0x01c4 1a3c mdctl15 module control 15 register (pci) 0x01c4 1a40 mdctl16 module control 16 register (mcbsp0) 0x01c4 1a44 ? reserved 0x01c4 1a48 mdctl18 module control 18 register (i2c) 0x01c4 1a4c mdctl19 module control 19 register (uart0) 0x01c4 1a50 ? reserved 0x01c4 1a54 ? reserved 0x01c4 1a58 ? reserved 0x01c4 1a5c mdctl23 module control 23 register (pwm0) 0x01c4 1a60 mdctl24 module control 24 register (pwm1) 0x01c4 1a64 mdctl25 module control 25 register (pwm2) 0x01c4 1a68 mdctl26 module control 26 register (gpio) 0x01c4 1a6c mdctl27 module control 27 register (timer0) 0x01c4 1a70 mdctl28 module control 28 register (timer1) 0x01c4 1a74 - 0x01c4 1a9b ? reserved 0x01c4 1a9c mdctl39 module control 39 register (c64x+ cpu) 0x01c4 1aa0 ? 0x01c4 1aa4 - 0x01c4 1fff ? reserved peripheral information and electrical specifications 152 submit documentation feedback
6.4 enhanced direct memory access (edma3) controller 6.4.1 edma3 channel synchronization events tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the edma controller handles all data transfers between memories and the device slave peripherals on the dm6433 device. these data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. these are summarized as follows: transfer to/from on-chip memories ? dsp l1d memory ? dsp l2 memory transfer to/from external storage ? ddr2 sdram ? nand flash ? asynchronous emif (emifa) transfer to/from peripherals/hosts ? vlynq ? hpi ? mcbsp0 ? mcasp0 ? pwm ? uart0 ? pci the edma supports two addressing modes: constant addressing and increment addressing. on the dm6433, constant addressing mode is not supported by any peripheral or internal memory. for more information on these two addressing modes, see the tms320dm643x dmp enhanced direct memory access (edma3) controller user's guide (literature number spru987 ). the edma supports up to 64 edma channels which service peripheral devices and external memory. table 6-6 lists the source of edma synchronization events associated with each of the programmable edma channels. for the dm6433 device, the association of an event to a channel is fixed; each of the edma channels has one specific event associated with it. these specific events are captured in the edma event registers (er, erh) even if the events are disabled by the edma event enable registers (eer, eerh). for more detailed information on the edma module and how edma events are enabled, captured, processed, linked, chained, and cleared, etc., see the tms320dm643x dmp enhanced direct memory access (edma3) controller user's guide (literature number spru987 ). table 6-6. dm6433 edma channel synchronization events (1) edma event name event description channel 0-1 ? reserved 2 xevt0 mcbsp0 transmit event 3 revt0 mcbsp0 receive event 4 ? reserved 5 ? reserved 6 ? reserved 7 ? reserved 8 ? reserved 9 rszevt vpss resizer event 10 axevte0 mcasp0 transmit event even (1) in addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. for more detailed information on edma event-transfer chaining, see the document support section for the enhanced direct memory access (edma) controller reference guide. submit documentation feedback peripheral information and electrical specifications 153
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-6. dm6433 edma channel synchronization events (continued) edma event name event description channel 11 axevto0 mcasp0 transmit event odd 12 axevt0 mcasp0 transmit event 13 arevte0 mcasp0 receive event even 14 arevto0 mcasp0 receive event odd 15 arevt0 mcasp0 receive event 16-21 ? reserved 22 urxevt0 uart 0 receive event 23 utxevt0 uart 0 transmit event 24 ? reserved 25 ? reserved 26 ? reserved 27 ? reserved 28 icrevt i2c receive event 29 icxevt i2c transmit event 30-31 ? reserved 32 gpint0 gpio 0 interrupt 33 gpint1 gpio 1 interrupt 34 gpint2 gpio 2 interrupt 35 gpint3 gpio 3 interrupt 36 gpint4 gpio 4 interrupt 37 gpint5 gpio 5 interrupt 38 gpint6 gpio 6 interrupt 39 gpint7 gpio 7 interrupt 40 gpbnkint0 gpio bank 0 interrupt 41 gpbnkint1 gpio bank 1 interrupt 42 gpbnkint2 gpio bank 2 interrupt 43 gpbnkint3 gpio bank 3 interrupt 44 gpbnkint4 gpio bank 4 interrupt 45 gpbnkint5 gpio bank 5 interrupt 46 gpbnkint6 gpio bank 6 interrupt 47 ? reserved 48 tevtl0 timer 0 event low interrupt 49 tevth0 timer 0 event high interrupt 50 tevtl1 timer 1 event low interrupt 51 tevth1 timer 1 evemt high interrupt 52 pwm0 pwm 0 event 53 pwm1 pwm 1 event 54 pwm2 pwm 2 event 55-63 ? reserved peripheral information and electrical specifications 154 submit documentation feedback
6.4.2 edma peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-7 lists the edma registers, their corresponding acronyms, and dm6433 device memory locations. table 6-7. dm6433 edma registers hex address acronym register name channel controller registers 0x01c0 0000 - 0x01c0 0003 reserved 0x01c0 0004 cccfg edma3cc configuration register 0x01c0 0008 - 0x01c0 01ff reserved global registers 0x01c0 0200 qchmap0 qdma channel 0 mapping to param register 0x01c0 0204 qchmap1 qdma channel 1 mapping to param register 0x01c0 0208 qchmap2 qdma channel 2 mapping to param register 0x01c0 020c qchmap3 qdma channel 3 mapping to param register 0x01c0 0210 qchmap4 qdma channel 4 mapping to param register 0x01c0 0214 qchmap5 qdma channel 5 mapping to param register 0x01c0 0218 qchmap6 qdma channel 6 mapping to param register 0x01c0 021c qchmap7 qdma channel 7 mapping to param register 0x01c0 0240 dmaqnum0 dma queue number register 0 (channels 00 to 07) 0x01c0 0244 dmaqnum1 dma queue number register 1 (channels 08 to 15) 0x01c0 0248 dmaqnum2 dma queue number register 2 (channels 16 to 23) 0x01c0 024c dmaqnum3 dma queue number register 3 (channels 24 to 31) 0x01c0 0250 dmaqnum4 dma queue number register 4 (channels 32 to 39) 0x01c0 0254 dmaqnum5 dma queue number register 5 (channels 40 to 47) 0x01c0 0258 dmaqnum6 dma queue number register 6 (channels 48 to 55) 0x01c0 025c dmaqnum7 dma queue number register 7 (channels 56 to 63) 0x01c0 0260 qdmaqnum cc qdma queue number 0x01c0 0264 - 0x01c0 0283 ? reserved 0x01c0 0284 quepri queue priority register 0x01c0 0288 - 0x01c0 02ff ? reserved 0x01c0 0300 emr event missed register 0x01c0 0304 emrh event missed register high 0x01c0 0308 emcr event missed clear register 0x01c0 030c emcrh event missed clear register high 0x01c0 0310 qemr qdma event missed register 0x01c0 0314 qemcr qdma event missed clear register 0x01c0 0318 ccerr edma3cc error register 0x01c0 031c ccerrclr edma3cc error clear register 0x01c0 0320 eeval error evaluate register 0x01c0 0340 drae0 dma region access enable register for region 0 0x01c0 0344 draeh0 dma region access enable register high for region 0 0x01c0 0348 drae1 dma region access enable register for region 1 0x01c0 034c draeh1 dma region access enable register high for region 1 0x01c0 0350 ? reserved 0x01c0 0354 ? reserved 0x01c0 0358 ? reserved 0x01c0 035c ? reserved 0x01c0 0360 - 0x01c0 037c ? reserved 0x01c0 0380 qrae0 qdma region access enable register for region 0 submit documentation feedback peripheral information and electrical specifications 155
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c0 0384 qrae1 qdma region access enable register for region 1 0x01c0 0388 ? reserved 0x01c0 038c ? reserved 0x01c0 0390 - 0x01c0 039c ? reserved 0x01c0 0400 q0e0 event q0 entry 0 register 0x01c0 0404 q0e1 event q0 entry 1 register 0x01c0 0408 q0e2 event q0 entry 2 register 0x01c0 040c q0e3 event q0 entry 3 register 0x01c0 0410 q0e4 event q0 entry 4 register 0x01c0 0414 q0e5 event q0 entry 5 register 0x01c0 0418 q0e6 event q0 entry 6 register 0x01c0 041c q0e7 event q0 entry 7 register 0x01c0 0420 q0e8 event q0 entry 8 register 0x01c0 0424 q0e9 event q0 entry 9 register 0x01c0 0428 q0e10 event q0 entry 10 register 0x01c0 042c q0e11 event q0 entry 11 register 0x01c0 0430 q0e12 event q0 entry 12 register 0x01c0 0434 q0e13 event q0 entry 13 register 0x01c0 0438 q0e14 event q0 entry 14 register 0x01c0 043c q0e15 event q0 entry 15 register 0x01c0 0440 q1e0 event q1 entry 0 register 0x01c0 0444 q1e1 event q1 entry 1 register 0x01c0 0448 q1e2 event q1 entry 2 register 0x01c0 044c q1e3 event q1 entry 3 register 0x01c0 0450 q1e4 event q1 entry 4 register 0x01c0 0454 q1e5 event q1 entry 5 register 0x01c0 0458 q1e6 event q1 entry 6 register 0x01c0 045c q1e7 event q1 entry 7 register 0x01c0 0460 q1e8 event q1 entry 8 register 0x01c0 0464 q1e9 event q1 entry 9 register 0x01c0 0468 q1e10 event q1 entry 10 register 0x01c0 046c q1e11 event q1 entry 11 register 0x01c0 0470 q1e12 event q1 entry 12 register 0x01c0 0474 q1e13 event q1 entry 13 register 0x01c0 0478 q1e14 event q1 entry 14 register 0x01c0 047c q1e15 event q1 entry 15 register 0x01c0 0480 q2e0 event q2 entry 0 register 0x01c0 0484 q2e1 event q2 entry 1 register 0x01c0 0488 q2e2 event q2 entry 2 register 0x01c0 048c q2e3 event q2 entry 3 register 0x01c0 0490 q2e4 event q2 entry 4 register 0x01c0 0494 q2e5 event q2 entry 5 register 0x01c0 0498 q2e6 event q2 entry 6 register 0x01c0 049c q2e7 event q2 entry 7 register 0x01c0 04a0 q2e8 event q2 entry 8 register 0x01c0 04a4 q2e9 event q2 entry 9 register 0x01c0 04a8 q2e10 event q2 entry 10 register peripheral information and electrical specifications 156 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c0 04ac q2e11 event q2 entry 11 register 0x01c0 04b0 q2e12 event q2 entry 12 register 0x01c0 04b4 q2e13 event q2 entry 13 register 0x01c0 04b8 q2e14 event q2 entry 14 register 0x01c0 04bc q2e15 event q2 entry 15 register 0x01c0 04c0 - 0x01c0 05ff reserved 0x01c0 0600 qstat0 queue 0 status register 0x01c0 0604 qstat1 queue 1 status register 0x01c0 0608 qstat2 queue 2 status register 0x01c0 060c - 0x01c0 061f reserved 0x01c0 0620 qwmthra queue watermark threshold a register for q[2:0] 0x01c0 0624 ? reserved 0x01c0 0640 ccstat edma3cc status register 0x01c0 0644 - 0x01c0 0fff reserved global channel registers 0x01c0 1000 er event register 0x01c0 1004 erh event register high 0x01c0 1008 ecr event clear register 0x01c0 100c ecrh event clear register high 0x01c0 1010 esr event set register 0x01c0 1014 esrh event set register high 0x01c0 1018 cer chained event register 0x01c0 101c cerh chained event register high 0x01c0 1020 eer event enable register 0x01c0 1024 eerh event enable register high 0x01c0 1028 eecr event enable clear register 0x01c0 102c eecrh event enable clear register high 0x01c0 1030 eesr event enable set register 0x01c0 1034 eesrh event enable set register high 0x01c0 1038 ser secondary event register 0x01c0 103c serh secondary event register high 0x01c0 1040 secr secondary event clear register 0x01c0 1044 secrh secondary event clear register high 0x01c0 1048 - 0x01c0 104f reserved 0x01c0 1050 ier interrupt enable register 0x01c0 1054 ierh interrupt enable register high 0x01c0 1058 iecr interrupt enable clear register 0x01c0 105c iecrh interrupt enable clear register high 0x01c0 1060 iesr interrupt enable set register 0x01c0 1064 iesrh interrupt enable set register high 0x01c0 1068 ipr interrupt pending register 0x01c0 106c iprh interrupt pending register high 0x01c0 1070 icr interrupt clear register 0x01c0 1074 icrh interrupt clear register high 0x01c0 1078 ieval interrupt evaluate register 0x01c0 1080 qer qdma event register 0x01c0 1084 qeer qdma event enable register submit documentation feedback peripheral information and electrical specifications 157
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c0 1088 qeecr qdma event enable clear register 0x01c0 108c qeesr qdma event enable set register 0x01c0 1090 qser qdma secondary event register 0x01c0 1094 qsecr qdma secondary event clear register 0x01c0 1098 - 0x01c0 1fff reserved shadow region 0 channel registers 0x01c0 2000 er event register 0x01c0 2004 erh event register high 0x01c0 2008 ecr event clear register 0x01c0 200c ecrh event clear register high 0x01c0 2010 esr event set register 0x01c0 2014 esrh event set register high 0x01c0 2018 cer chained event register 0x01c0 201c cerh chained event register high 0x01c0 2020 eer event enable register 0x01c0 2024 eerh event enable register high 0x01c0 2028 eecr event enable clear register 0x01c0 202c eecrh event enable clear register high 0x01c0 2030 eesr event enable set register 0x01c0 2034 eesrh event enable set register high 0x01c0 2038 ser secondary event register 0x01c0 203c serh secondary event register high 0x01c0 2040 secr secondary event clear register 0x01c0 2044 secrh secondary event clear register high 0x01c0 2048 - 0x01c0 204c - reserved 0x01c0 2050 ier interrupt enable register 0x01c0 2054 ierh interrupt enable register high 0x01c0 2058 iecr interrupt enable clear register 0x01c0 205c iecrh interrupt enable clear register high 0x01c0 2060 iesr interrupt enable set register 0x01c0 2064 iesrh interrupt enable set register high 0x01c0 2068 ipr interrupt pending register 0x01c0 206c iprh interrupt pending register high 0x01c0 2070 icr interrupt clear register 0x01c0 2074 icrh interrupt clear register high 0x01c0 2078 ieval interrupt evaluate register 0x01c0 207c - reserved 0x01c0 2080 qer qdma event register 0x01c0 2084 qeer qdma event enable register 0x01c0 2088 qeecr qdma event enable clear register 0x01c0 208c qeesr qdma event enable set register 0x01c0 2090 qser qdma secondary event register 0x01c0 2094 qsecr qdma secondary event clear register 0x01c0 2098 - 0x01c0 21fc - reserved shadow region 1 channel registers 0x01c0 2200 er event register 0x01c0 2204 erh event register high peripheral information and electrical specifications 158 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c0 2208 ecr event clear register 0x01c0 220c ecrh event clear register high 0x01c0 2210 esr event set register 0x01c0 2214 esrh event set register high 0x01c0 2218 cer chained event register 0x01c0 221c cerh chained event register high 0x01c0 2220 eer event enable register 0x01c0 2224 eerh event enable register high 0x01c0 2228 eecr event enable clear register 0x01c0 222c eecrh event enable clear register high 0x01c0 2230 eesr event enable set register 0x01c0 2234 eesrh event enable set register high 0x01c0 2238 ser secondary event register 0x01c0 223c serh secondary event register high 0x01c0 2240 secr secondary event clear register 0x01c0 2244 secrh secondary event clear register high 0x01c0 2248 - 0x01c0 224c - reserved 0x01c0 2250 ier interrupt enable register 0x01c0 2254 ierh interrupt enable register high 0x01c0 2258 iecr interrupt enable clear register 0x01c0 225c iecrh interrupt enable clear register high 0x01c0 2260 iesr interrupt enable set register 0x01c0 2264 iesrh interrupt enable set register high 0x01c0 2268 ipr interrupt pending register 0x01c0 226c iprh interrupt pending register high 0x01c0 2270 icr interrupt clear register 0x01c0 2274 icrh interrupt clear register high 0x01c0 2278 ieval interrupt evaluate register 0x01c0 227c - reserved 0x01c0 2280 qer qdma event register 0x01c0 2284 qeer qdma event enable register 0x01c0 2288 qeecr qdma event enable clear register 0x01c0 228c qeesr qdma event enable set register 0x01c0 2290 qser qdma secondary event register 0x01c0 2294 qsecr qdma secondary event clear register 0x01c0 2298 - 0x01c0 23fc - reserved 0x01c0 2400 - 0x01c0 25fc - reserved 0x01c0 2600 - 0x01c0 27fc - reserved 0x01c0 2800 - 0x01c0 29fc - reserved 0x01c0 2a00 - 0x01c0 2bfc - reserved 0x01c0 2c00 - 0x01c0 2dfc - reserved 0x01c0 2e00 - 0x01c0 2ffc - reserved 0x01c0 2ffd - 0x01c0 3fff - reserved 0x01c0 4000 - 0x01c0 4fff - parameter set ram (see table 6-8 ) 0x01c0 5000 - 0x01c0 7fff - reserved 0x01c0 8000 - 0x01c0 ffff - reserved transfer controller 0 registers submit documentation feedback peripheral information and electrical specifications 159
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c1 0000 - reserved 0x01c1 0004 tccfg edma3 tc0 configuration register 0x01c1 0008 - 0x01c1 00ff - reserved 0x01c1 0100 tcstat edma3 tc0 channel status register 0x01c1 0104 - 0x01c1 0110 - reserved 0x01c1 0114 - 0x01c1 011f - reserved 0x01c1 0120 errstat edma3 tc0 error status register 0x01c1 0124 erren edma3 tc0 error enable register 0x01c1 0128 errclr edma3 tc0 error clear register 0x01c1 012c errdet edma3 tc0 error details register 0x01c1 0130 errcmd edma3 tc0 error interrupt command register 0x01c1 0134 - 0x01c1 013f - reserved 0x01c1 0140 rdrate edma3 tc0 read command rate register 0x01c1 0144 - 0x01c1 01ff - reserved 0x01c1 0200 - 0x01c1 023f - reserved 0x01c1 0240 saopt edma3 tc0 source active options register 0x01c1 0244 sasrc edma3 tc0 source active source address register 0x01c1 0248 sacnt edma3 tc0 source active count register 0x01c1 024c sadst edma3 tc0 source active destination address register 0x01c1 0250 sabidx edma3 tc0 active b-index register 0x01c1 0254 sampprxy edma3 tc0 source active memory protection proxy register 0x01c1 0258 sacntrld edma3 tc0 source active count reload register 0x01c1 025c sasrcbref edma3 tc0 source active source address b-reference register 0x01c1 0260 sadstbref edma3 tc0 source active destination address b-reference register 0x01c1 0264 - 0x01c1 027f - reserved 0x01c1 0280 dfcntrld edma3 tc0 destination fifo set count reload register 0x01c1 0284 dfsrcbref edma3 tc0 destination fifo set source address b-reference register edma3 tc0 destination fifo set destination address b-reference 0x01c1 0288 dfdstbref register 0x01c1 028c - 0x01c1 02ff - reserved 0x01c1 0300 dfopt0 edma3 tc0 destination fifo options register 0 0x01c1 0304 dfsrc0 edma3 tc0 destination fifo source address register 0 0x01c1 0308 dfcnt0 edma3 tc0 destination fifo count register 0 0x01c1 030c dfdst0 edma3 tc0 destination fifo destination address register 0 0x01c1 0310 dfbidx0 edma3 tc0 destination fifo b-index register 0 0x01c1 0314 dfmpprxy0 edma3 tc0 destination fifo memory protection proxy register 0 0x01c1 0318 - 0x01c1 033f - reserved 0x01c1 0340 dfopt1 edma3 tc0 destination fifo options register 1 0x01c1 0344 dfsrc1 edma3 tc0 destination fifo source address register 1 0x01c1 0348 dfcnt1 edma3 tc0 destination fifo count register 1 0x01c1 034c dfdst1 edma3 tc0 destination fifo destination address register 1 0x01c1 0350 dfbidx1 edma3 tc0 destination fifo b-index register 1 0x01c1 0354 dfmpprxy1 edma3 tc0 destination fifo memory protection proxy register 1 0x01c1 0358 - 0x01c1 037f - reserved 0x01c1 0380 dfopt2 edma3 tc0 destination fifo options register 2 0x01c1 0384 dfsrc2 edma3 tc0 destination fifo source address register 2 0x01c1 0388 dfcnt2 edma3 tc0 destination fifo count register 2 peripheral information and electrical specifications 160 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c1 038c dfdst2 edma3 tc0 destination fifo destination address register 2 0x01c1 0390 dfbidx2 edma3 tc0 destination fifo b-index register 2 0x01c1 0394 dfmpprxy2 edma3 tc0 destination fifo memory protection proxy register 2 0x01c1 0398 - 0x01c1 03bf - reserved 0x01c1 03c0 dfopt3 edma3 tc0 destination fifo options register 3 0x01c1 03c4 dfsrc3 edma3 tc0 destination fifo source address register 3 0x01c1 03c8 dfcnt3 edma3 tc0 destination fifo count register 3 0x01c1 03cc dfdst3 edma3 tc0 destination fifo destination address register 3 0x01c1 03d0 dfbidx3 edma3 tc0 destination fifo b-index register 3 0x01c1 03d4 dfmpprxy3 edma3 tc0 destination fifo memory protection proxy register 3 0x01c1 03d8 - 0x01c1 03ff - reserved transfer controller 1 registers 0x01c1 0400 - reserved 0x01c1 0404 tccfg edma3 tc1 configuration register 0x01c1 0408 - 0x01c1 04ff - reserved 0x01c1 0500 tcstat edma3 tc1 channel status register 0x01c1 0504 - 0x01c1 0510 - reserved 0x01c1 0514 - 0x01c1 051f - reserved 0x01c1 0520 errstat edma3 tc1 error status register 0x01c1 0524 erren edma3 tc1 error enable register 0x01c1 0528 errclr edma3 tc1 error clear register 0x01c1 052c errdet edma3 tc1 error details register 0x01c1 0530 errcmd edma3 tc1 error interrupt command register 0x01c1 0534 - 0x01c1 053f - reserved 0x01c1 0540 rdrate edma3 tc1 read command rate register 0x01c1 0544 - 0x01c1 05ff - reserved 0x01c1 0600 - 0x01c1 063f - reserved 0x01c1 0640 saopt edma3 tc1 source active options register 0x01c1 0644 sasrc edma3 tc1 source active source address register 0x01c1 0648 sacnt edma3 tc1 source active count register 0x01c1 064c sadst edma3 tc1 source active destination address register 0x01c1 0650 sabidx edma3 tc1 active b-index register 0x01c1 0654 sampprxy edma3 tc1 source active memory protection proxy register 0x01c1 0658 sacntrld edma3 tc1 source active count reload register 0x01c1 065c sasrcbref edma3 tc1 source active source address b-reference register 0x01c1 0660 sadstbref edma3 tc1 source active destination address b-reference register 0x01c1 0664 - 0x01c1 067f - reserved 0x01c1 0680 dfcntrld edma3 tc1 destination fifo set count reload register 0x01c1 0684 dfsrcbref edma3 tc1 destination fifo set source address b-reference register edma3 tc1 destination fifo set destination address b-reference 0x01c1 0688 dfdstbref register 0x01c1 068c - 0x01c1 06ff - reserved 0x01c1 0700 dfopt0 edma3 tc1 destination fifo options register 0 0x01c1 0704 dfsrc0 edma3 tc1 destination fifo source address register 0 0x01c1 0708 dfcnt0 edma3 tc1 destination fifo count register 0 0x01c1 070c dfdst0 edma3 tc1 destination fifo destination address register 0 0x01c1 0710 dfbidx0 edma3 tc1 destination fifo b-index register 0 submit documentation feedback peripheral information and electrical specifications 161
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c1 0714 dfmpprxy0 edma3 tc1 destination fifo memory protection proxy register 0 0x01c1 0718 - 0x01c1 073f - reserved 0x01c1 0740 dfopt1 edma3 tc1 destination fifo options register 1 0x01c1 0744 dfsrc1 edma3 tc1 destination fifo source address register 1 0x01c1 0748 dfcnt1 edma3 tc1 destination fifo count register 1 0x01c1 074c dfdst1 edma3 tc1 destination fifo destination address register 1 0x01c1 0750 dfbidx1 edma3 tc1 destination fifo b-index register 1 0x01c1 0754 dfmpprxy1 edma3 tc1 destination fifo memory protection proxy register 1 0x01c1 0758 - 0x01c1 077f - reserved 0x01c1 0780 dfopt2 edma3 tc1 destination fifo options register 2 0x01c1 0784 dfsrc2 edma3 tc1 destination fifo source address register 2 0x01c1 0788 dfcnt2 edma3 tc1 destination fifo count register 2 0x01c1 078c dfdst2 edma3 tc1 destination fifo destination address register 2 0x01c1 0790 dfbidx2 edma3 tc1 destination fifo b-index register 2 0x01c1 0794 dfmpprxy2 edma3 tc1 destination fifo memory protection proxy register 2 0x01c1 0798 - 0x01c1 07bf - reserved 0x01c1 07c0 dfopt3 edma3 tc1 destination fifo options register 3 0x01c1 07c4 dfsrc3 edma3 tc1 destination fifo source address register 3 0x01c1 07c8 dfcnt3 edma3 tc1 destination fifo count register 3 0x01c1 07cc dfdst3 edma3 tc1 destination fifo destination address register 3 0x01c1 07d0 dfbidx3 edma3 tc1 destination fifo b-index register 3 0x01c1 07d4 dfmpprxy3 edma3 tc1 destination fifo memory protection proxy register 3 0x01c1 07d8 - 0x01c1 07ff - reserved transfer controller 2 registers 0x01c1 0800 - reserved 0x01c1 0804 tccfg edma3 tc2 configuration register 0x01c1 0808 - 0x01c1 08ff - reserved 0x01c1 0900 tcstat edma3 tc2 channel status register 0x01c1 0904 - 0x01c1 0910 - reserved 0x01c1 0914 - 0x01c1 091f - reserved 0x01c1 0920 errstat edma3 tc2 error status register 0x01c1 0924 erren edma3 tc2 error enable register 0x01c1 0928 errclr edma3 tc2 error clear register 0x01c1 092c errdet edma3 tc2 error details register 0x01c1 0930 errcmd edma3 tc2 error interrupt command register 0x01c1 0934 - 0x01c1 093f - reserved 0x01c1 0940 rdrate edma3 tc2 read command rate register 0x01c1 0944 - 0x01c1 09ff - reserved 0x01c1 0a00 - 0x01c1 0a3f - reserved 0x01c1 0a40 saopt edma3 tc2 source active options register 0x01c1 0a44 sasrc edma3 tc2 source active source address register 0x01c1 0a48 sacnt edma3 tc2 source active count register 0x01c1 0a4c sadst edma3 tc2 source active destination address register 0x01c1 0a50 sabidx edma3 tc2 active b-index register 0x01c1 0a54 sampprxy edma3 tc2 source active memory protection proxy register 0x01c1 0a58 sacntrld edma3 tc2 source active count reload register 0x01c1 0a5c sasrcbref edma3 tc2 source active source address b-reference register peripheral information and electrical specifications 162 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-7. dm6433 edma registers (continued) hex address acronym register name 0x01c1 0a60 sadstbref edma3 tc2 source active destination address b-reference register 0x01c1 0a64 - 0x01c1 0a7f - reserved 0x01c1 0a80 dfcntrld edma3 tc2 destination fifo set count reload register 0x01c1 0a84 dfsrcbref edma3 tc2 destination fifo set source address b-reference register edma3 tc2 destination fifo set destination address b-reference 0x01c1 0a88 dfdstbref register 0x01c1 0a8c - 0x01c1 0aff - reserved 0x01c1 0b00 dfopt0 edma3 tc2 destination fifo options register 0 0x01c1 0b04 dfsrc0 edma3 tc2 destination fifo source address register 0 0x01c1 0b08 dfcnt0 edma3 tc2 destination fifo count register 0 0x01c1 0b0c dfdst0 edma3 tc2 destination fifo destination address register 0 0x01c1 0b10 dfbidx0 edma3 tc2 destination fifo b-index register 0 0x01c1 0b14 dfmpprxy0 edma3 tc2 destination fifo memory protection proxy register 0 0x01c1 0b18 - 0x01c1 0b3f - reserved 0x01c1 0b40 dfopt1 edma3 tc2 destination fifo options register 1 0x01c1 0b44 dfsrc1 edma3 tc2 destination fifo source address register 1 0x01c1 0b48 dfcnt1 edma3 tc2 destination fifo count register 1 0x01c1 0b4c dfdst1 edma3 tc2 destination fifo destination address register 1 0x01c1 0b50 dfbidx1 edma3 tc2 destination fifo b-index register 1 0x01c1 0b54 dfmpprxy1 edma3 tc2 destination fifo memory protection proxy register 1 0x01c1 0b58 - 0x01c1 0b7f - reserved 0x01c1 0b80 dfopt2 edma3 tc2 destination fifo options register 2 0x01c1 0b84 dfsrc2 edma3 tc2 destination fifo source address register 2 0x01c1 0b88 dfcnt2 edma3 tc2 destination fifo count register 2 0x01c1 0b8c dfdst2 edma3 tc2 destination fifo destination address register 2 0x01c1 0b90 dfbidx2 edma3 tc2 destination fifo b-index register 2 0x01c1 0b94 dfmpprxy2 edma3 tc2 destination fifo memory protection proxy register 2 0x01c1 0b98 - 0x01c1 0bbf - reserved 0x01c1 0bc0 dfopt3 edma3 tc2 destination fifo options register 3 0x01c1 0bc4 dfsrc3 edma3 tc2 destination fifo source address register 3 0x01c1 0bc8 dfcnt3 edma3 tc2 destination fifo count register 3 0x01c1 0bcc dfdst3 edma3 tc2 destination fifo destination address register 3 0x01c1 0bd0 dfbidx3 edma3 tc2 destination fifo b-index register 3 0x01c1 0bd4 dfmpprxy3 edma3 tc2 destination fifo memory protection proxy register 3 0x01c1 0bd8 - 0x01c1 0bff - reserved table 6-8 shows an abbreviation of the set of registers which make up the parameter set for each of 128 edma events. each of the parameter register sets consist of 8 32-bit word entries. table 6-9 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. submit documentation feedback peripheral information and electrical specifications 163
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-8. edma parameter set ram hex address range description 0x01c0 4000 - 0x01c0 401f parameters set 0 (8 32-bit words) 0x01c0 4020 - 0x01c0 403f parameters set 1 (8 32-bit words) 0x01c0 4040 - 0x01c0 405f parameters set 2 (8 32-bit words) 0x01c0 4060 - 0x01c0 407f parameters set 3 (8 32-bit words) 0x01c0 4080 - 0x01c0 409f parameters set 4 (8 32-bit words) 0x01c0 40a0 - 0x01c0 40bf parameters set 5 (8 32-bit words) ... ... 0x01c0 4fc0 - 0x01c0 4fdf parameters set 126 (8 32-bit words) 0x01c0 4fe0 - 0x01c0 4fff parameters set 127 (8 32-bit words) table 6-9. parameter set entries hex offset address acronym parameter entry within the parameter set 0x0000 opt option 0x0004 src source address 0x0008 a_b_cnt a count, b count 0x000c dst destination address 0x0010 src_dst_bidx source b index, destination b index 0x0014 link_bcntrld link address, b count reload 0x0018 src_dst_cidx source c index, destination c index 0x001c ccnt c count peripheral information and electrical specifications 164 submit documentation feedback
6.5 reset 6.5.1 power-on reset ( por pin) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the reset controller detects the different type of resets supported on the dm6433 device and manages the distribution of those resets throughout the device. the dm6433 device has several types of device-level global resets - power-on reset, warm reset, and max reset. table 6-10 explains further the types of reset, the reset initiator, and the effects of each reset on the chip. see section 6.5.9 , reset electrical data/timing, for more information on the effects of each reset on the pll controllers and their clocks. table 6-10. device-level global reset types type initiator effect(s) por pin global chip reset (cold reset). activates the por signal on chip, which resets the entire chip including the emulation logic. power-on reset the power-on reset ( por) pin must be driven low during power (por) ramp of the device. device boot and configuration pin are latched. resets everything except for the emulation logic. emulator stays warm reset reset pin alive during warm reset. device boot and configuration pin are latched. same as a warm reset, except the dm6433 device boot and max reset emulator, wd timer (timer 2) configuration pins are not re-latched. in addition to device-level global resets, the psc provides the capability to cause local resets to peripherals and/or the cpu. power-on reset (por) is initiated by the por pin and is used to reset the entire chip, including the emulation logic. power-on reset is also referred to as a cold reset since the device usually goes through a power-up cycle. during power-up, the por pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. if an external 27-mhz oscillator is used on the mxi/clkin pin, the source clock should also be running at the correct frequency prior to de-asserting the por pin. note: a device power-up cycle is not required to initiate a power-on reset. the following sequence must be followed during a power-on reset. 1. wait for the power supplies to reach normal operating conditions while keeping the por pin asserted (driven low). 2. wait for the input clock source to be stable while keeping the por pin asserted (low). 3. once the power supplies and the input clock source are stable, the por pin must remain asserted (low) for a minimum of 12 mxi cycles. within the low period of the por pin, the following happens: ? the reset signals flow to the entire chip (including the emulation logic), resetting the modules on chip. ? the pll controller clocks start at the frequency of the mxi clock. the clocks are propagated throughout the chip to reset the chip synchronously. by default, both pll1 and pll2 are in reset and unlocked. the pll controllers default to pll bypass mode. ? the resetout pin stays asserted (low), indicating the device is in reset. 4. the por pin may now be deasserted (driven high). when the por pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 5. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). at this point: submit documentation feedback peripheral information and electrical specifications 165
6.5.1.1 usage of por versus reset pins 6.5.1.2 latching boot and configuration pins 6.5.2 warm reset ( reset pin) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. por and reset are independent resets. if the device needs to go through a power-up cycle, por ( not reset) must be used to fully reset the device. in functional end-system, emulation/debugger logic is typically not needed; therefore, the recommendation for functional end-system is to use the por pin for full device reset. if reset pin is not needed, it can be pulled inactive (high) via an external pullup resistor. in a debug system, it is typically desirable to allow the reset of the device without crashing an emulation session. in this case, the user can use the por pin to achieve full device reset and use the reset pin to achieve a debug reset?which resets the entire device except emulation logic. internal to the chip, the two device reset pins reset and por are logically and?d together only for the purpose of latching device boot and configuration pins. the values on all device and boot configuration pins are latched into the bootcfg register when the logical and of reset and por transitions from low-to-high. a warm reset is activated by driving the reset pin active low. this resets everything in the device except the emulation logic. an emulator session will stay alive during warm reset. for more information on por vs. reset usage, see section 6.5.1.1 , usage of por versus reset pins and section 6.5.1.2 , latching boot and configuration pins. the following sequence must be followed during a warm reset: 1. power supplies and input clock source should already be stable. 2. the reset pin must be asserted (low) for a minimum of 12 mxi cycles. within the low period of the reset pin, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip, except the emulation logic. ? the pll controllers are reset thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. ? the resetout pin becomes asserted (low), indicating the device is in reset. 3. the reset pin may now be deasserted (driven high). when the reset pin is deasserted (high), the configuration pin values are latched and the pll controllers changed their system clocks to their default divide-down values. both pll controllers are still in pll bypass mode. other device initialization also begins. 4. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). peripheral information and electrical specifications 166 submit documentation feedback
6.5.3 maximum reset tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 )). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. a maximum (max) reset is initiated by the emulator or the watchdog timer (timer 2). the effects are the same as a warm reset, except the device boot and configuration pins are not re-latched. the emulator initiates a maximum reset via the icepick module. this icepick initiated reset is non-maskable. when the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway condition. the watchdog timeout reset condition is masked if the timerctl.wdrst bit is cleared to "0". to invoke the maximum reset via the icepick module, the user can perform the following from the code composer studio? ide menu: debug ? advanced resets ? system reset this is the max reset sequence: 1. max reset is initiated by the emulator or the watchdog timer. during this time, the following happens: ? the reset signals flow to the entire chip resetting all the modules on chip except the emulation logic. ? the pll controllers are reset thereby, switching back to pll bypass mode and resetting all their registers to default values. both pll1 and pll2 are placed in reset and lose lock. ? the resetout pin becomes asserted (low), indicating the device is in reset. 2. after device initialization is complete, the pll controllers pause the system clocks for 10 cycles. at the end of these 10 cycles, the resetout pin is deasserted (driven high). at this point: ? the i/o pins are controlled by the default peripherals (default peripherals are determined by pinmux0 and pinmux1 registers). ? the clock and reset of each peripheral is determined by the default settings of the power and sleep controller (psc). ? the pll controllers are operating in pll bypass mode. ? the c64x+ begins executing from dspbootaddr (determined by bootmode selection). after the reset sequence, the boot sequence begins. since the boot and configuration pins are not latched with a max reset, the previous values (as shown in the bootcfg register) are used to select the boot mode. for more details on the boot sequence, see the using the tms320dm643x bootloader application report (literature number spraag0 ). after the boot sequence, follow the software initialization sequence described in section 3.8 , device initialization sequence after reset. submit documentation feedback peripheral information and electrical specifications 167
6.5.4 cpu local reset 6.5.5 peripheral local reset 6.5.6 reset priority 6.5.7 reset controller register 6.5.8 pin behaviors at reset tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the c64x+ dsp cpu has an internal reset input that allows a host (pci/hpi) to control it. this reset is configured through a register bit (mdctl[39]. lrst) in the power sleep controller (psc) module. when in c64x+ local reset, the slave dma port on c64x+ will remain active and the internal memory will be accessible. for procedures on asserting and de-asserting cpu local reset by the host, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). for information on peripheral selection at the rising edge of por or reset, see section 3 , device configurations of this data manual. the user can configure the local reset and clock state of a peripheral through programming the psc. table 6-4 , dm6433 lpsc assignments identifies the lpsc numbers and the peripherals capable of being locally reset by the psc. for more detailed information on the programming of these peripherals by the psc, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). if any of the above reset sources occur simultaneously, the pllc only processes the highest priority reset request. the reset request priorities are as follows (high to low): power-on reset maximum reset warm reset cpu reset the reset type status (rstype) register (01c4 00e4) is the only register for the reset controller. this register falls in the same memory range as the pll1 controller registers (see table 6-18 for the pll1 controller registers (including reset controller)). for more details on the rstype register, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). during normal operations, pins are controlled by the respective peripheral selected in the pinmux0 or pinmux1 register. during device level global reset, the pin behaves as follows: multiplexed boot and configuration pins these pins are forced 3-stated when resetout is asserted (low). this is to ensure the proper boot and configuration values can be latched on these multiplexed pins. this is particularly useful in the case where the boot and configuration values are driven by an external control device. after resetout is deasserted (high), these pins are controlled by their respective default peripheral. boot and configuration pins group: yout6/gp[28], yout5/gp[27], yout4/gp[26]/(fastboot), yout3/gp[25]/(bootmode3), yout2/gp[24]/(bootmode2), yout1/gp[23]/(bootmode1), yout0/gp[22]/(bootmode0), r0/em_a[4]/gp[10]/(aeaw2/pllms2), g1/em_a[1]/(ale)/gp[9]/(aeaw1/pllms1), b1/em_a[2]/(cle)/gp[8]/(aeaw0/pllms0), r1/em_a[0]/gp[7]/(aem2), r2/em_ba[0]/gp[6]/(aem1), and b2/em_ba[1]/gp[5]/(aem0). for information on whether external pullup/pulldown resistors should be used on the boot and configuration pins, see section 3.9.1 , pullup/pulldown resistors. 168 peripheral information and electrical specifications submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 default power down pins as discussed in section 3.2 , power considerations, the vdd3p3v_pwdn register controls power to the 3.3-v pins. the vdd3p3v_pwdn register defaults to powering down some 3.3-v pins to save power. for more details on the vdd3p3v_pwdn register and which 3.3-v pins default to powerup or powerdown, section 3.2 , power considerations. the pins that default to powerdown, are both reset to powerdown and high-impedance. they remain in that state until configured otherwise by vdd3p3_pwdn and pinmux0/pinmux1 programming. default power down pin group: gp[4]/pwm1, aclkr0/clkx0/gp[99], afsr0/dr0/gp[100], ahclkr0/clkr0/gp[101], axr0[3]/fsr0/gp[102], axr0[2]/fsx0/gp[103], axr0[1]/dx0/gp[104], axr0/gp[105], aclkx0/gp[106], afsx0/gp[107], ahclkx0/gp[108], amutein0/gp[109], amute0/gp[110], tout1l/gp[55], tinp1l/gp[56], clks0/tout0l/gp[97], tinp0l/gp[98], urxd0/gp[85], utxd0/gp[86], ucts0/gp[87], and urts0/pwm0/gp[88]. all other pins during resetout assertion (low), all other pins are controlled by the default peripheral. the default peripheral is determined by the default settings of the pinmux0 or pinmux1 registers. some of the pinmux0/pinmux1 settings are determined by configuration pins latched at reset. to determine the reset behavior of these pins, see section 3.7 , multiplexed pin configurations and read the rest of the this subsection to understand how that default peripheral controls the pin. the reset behaviors for all these other pins are categorized as follows (also see figure 6-7 and figure 6-8 in section 6.5.9 , reset electrical data/timing): z+/low group (z longer-to-low group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive a logic low. z+/high group (z longer-to-high group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive a logic high. z+/invalid group (z longer-to-invalid group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins drive an invalid value until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). z group: these pins are 3-stated by default, and these pins remain 3-stated throughout resetout assertion. when resetout is deasserted, these pins remain 3-stated until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). low group: these pins are low by default, and remain low until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). high group: these pins are high by default, and remain high until configured otherwise by their respective peripheral (after the peripheral is enabled by the psc). z/low group (z-to-low group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. when the reset source is deasserted, these pins drive a logic low. z/high group (z-to-high group): these pins are 3-stated when device-level global reset source (e.g., por, reset, or max reset) is asserted. when reset source is deasserted, these pins drive a logic high. clock group: these clock pins are toggling by default. they paused momentarily before resetout is deasserted (high). the only pin in the clock group is clkout0. this is a list of possible default peripherals and how they control the pins during reset: gpio: all gpio pins behave according to z group. note: the following emifa list only includes pins that can default to function as emifa signals. emifa: these emifa signals are multiplexed with boot and configuration pins: em_a[4], em_a[2:0], submit documentation feedback peripheral information and electrical specifications 169
6.5.9 reset electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com em_ba[0], em_ba[1]; therefore, they are forced 3-stated throughout resetout. ? z+/low group: em_a[4], em_a[2:0] ? z+/high group: em_ba[0], em_ba[1], em_oe, em_we ? z+/invalid group:em_d[7:0] ? z/low group: em_a[21:5], em_a[3], em_r/ w ? z/high group: em_cs2 ? z group: em_wait/(rdy/ bsy) ddr2 memory controller: ? clock group: ddr_clk, ddr_clk ? ddr2 z group: ddr_dqm[3:0], ddr_dqs[3:0], ddr_d[31:0] ? ddr2 low group: ddr_cke, ddr_ba[2:0], ddr_a[12:0] ? ddr2 high group: ddr_cs, ddr_we, ddr_ras, ddr_cas pci: all pci pins behave according to z group. i2c: all i2c pins behave according to z group. jtag: tdo, emu0, and emu1 pins behave according to z group. tck, tdi, tms, and trst are input-only pins. clock: clkout0 for more information on the pin behaviors during device-level global reset, see figure 6-7 and figure 6-8 in section 6.5.9 , reset electrical data/timing. note: if a configuration pin must be routed out from the device, the internal pullup/pulldown (ipu/ipd) resistor should not be relied upon; ti recommends the use of an external pullup/pulldown resistor. table 6-11. timing requirements for reset (see figure 6-7 and figure 6-8 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t w(reset) pulse duration, por low or reset low 12c (1) ns setup time, boot and configuration pins valid before por high or reset 4 t su(config) 12c (1) ns high (2) hold time, boot and configuration pins valid after por high or reset 5 t h(config) 0 ns high (2) (1) c = 1/mxi clock frequency in ns. the device clock source must be stable and at a valid frequency prior to meeting the t w(reset) requirement. (2) for the list of boot and configuration pins, see table 2-5 , boot terminal functions. table 6-12. switching characteristics over recommended operating conditions during reset (1) (see figure 6-8 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 2 t d(rsth-rstouth) delay time, por high or reset high to resetout high 1900c ns 3 t w(pause) pulse duration, sysclks paused (low) before resetout high 10c 10c ns 6 t d(rstl-iv) delay time, por low or reset low to pins invalid 20 ns 7 t d(rsth-v) delay time, por high or reset high to pins valid 20 ns 8 t d(rstouth-v) delay time, resetout high to pins valid 0 ns 9 t d(rstouth-iv) delay time, resetout high to pins invalid 12c ns (1) c = 1/clkin1 clock frequency in ns. peripheral information and electrical specifications 170 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-7 shows the power-up timing. figure 6-8 shows the warm reset ( reset) timing. max reset timing is identical to warm reset timing, except the boot and configuration pins are not relatched and the bootcfg register retains its previous value latched before the max reset was initiated. submit documentation feedback peripheral information and electrical specifications 171
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com a. power supplies and mxi must be stable before the start of t w(reset). . b. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 6.5.8 , pin behaviors at reset. figure 6-7. power-up timing (b) peripheral information and electrical specifications 172 submit documentation feedback mxi (a) por reset resetout sysclkrefclk (pllc1) sysclk1 sysclk2 sysclk3 clkout0 boot and configuration pins config z+/low group (z longer-to-low) z+/high group (z longer-to-low) z group power supplies ramping power supplies stable hi-zhi-z hi-z clock source stable 1 4 5 2 3 88 8 ddr2 z group ddr2 low group ddr2 high group driven or hi-z z/high group (z-to-high) z/low group (z-to-low) 7 7 7 7 7 z+/invalid group (z longer-to-invalid) hi-z 9 invalid
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 a. pin reset behavior depends on which peripheral defaults to controlling the multiplexed pin. for more details on what pin group (e.g., z group, z/low group, z/high group, etc.) each pin belongs to, see section 6.5.8 , pin behaviors at reset. figure 6-8. warm reset ( reset) timing (a) submit documentation feedback peripheral information and electrical specifications 173 mxi por reset resetout sysclkrefclk (pllc1) sysclk1 sysclk2 sysclk3 clkout0 boot and configuration pins config power supplies stable 1 4 5 2 3 pll1 clock div1 clockdiv3 clock div6 clock driven or hi-z 8 6 driven or hi-z z+/low group (z longer-to-low) z+/high group (z longer-to-high) z group 8 ddr2 z group ddr2 low group ddr2 high group z/high group (z-to-high) 7 z/low group (z-to-low) 7 driven or hi-z driven or hi-zdriven or hi-z 66 6 6 6 8 z+/invalid group (z longer-to-invalid) 9 invalid
6.6 external clock input from mxi/clkin pin 6.6.1 clock input option 1?crystal tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dm6433 device includes two options to provide an external clock input: use an on-chip oscillator with external crystal. use an external 1.8-v lvcmos-compatible clock input. the optimal external clock input frequency is 27 mhz. section 6.6.1 provides more details on option 1, using an on-chip oscillator with external crystal. section 6.6.2 provides details on option 2, using an external 1.8-v lvcmos-compatible clock input. in this option, a crystal is used as the external clock input to the dm6433. the 27-mhz oscillator provides the reference clock for all dm6433 subsystems and peripherals. the on-chip oscillator requires an external 27-mhz crystal connected across the mxi and mxo pins, along with two load capacitors, as shown in figure 6-9 . the external crystal load capacitors must be connected only to the 27-mhz oscillator ground pin (mxv ss ). do not connect to board ground (v ss ). the mxv dd pin can be connected to the same 1.8 v power supply as dv ddr2 . figure 6-9. 27-mhz system oscillator the load capacitors, c1 and c2, should be chosen such that the equation is satisfied (typical values are c1 = c2 = 10 pf). c l in the equation is the load specified by the crystal manufacturer. all discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (mxi and mxo) and to the mxv ss pin. table 6-13. input requirements for crystal parameter min typ max unit start-up time (from power up until oscillating at stable frequency of 27 4 ms mhz) oscillaton frequency 27 mhz esr 60 w frequency stability (1) 50 ppm (1) applies only when using the vpbe for ntsc or pal compliant video. for video and audio applications, stability of the input clock is very important. the user should select crystals with low enough ppm to ensure good video and audio quality for the specific application. if the vpbe is used for ntsc or pal compliant video output, ti recommends a 27-mhz, 50-ppm crystal. for more details on this ntsc and pal compliant output video, see section 6.10.2 , video processing back-end (vpbe). peripheral information and electrical specifications 174 submit documentation feedback mxi/clkin mxo c1 c2 crystal 27 mhz mxv ss 1.8 v mxv dd c l c 1 c 2 ( c 1 c 2 )
6.6.2 clock input option 2?1.8-v lvcmos-compatible clock input tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 in this option, a 1.8-v lvcmos-compatible clock input is used as the external clock input to the dm6433. the external connections are shown in figure 6-10 . the mxi/clkin pin is connected to the 1.8-v lvcmos-compatible clock source. the mxo pin is left unconnected. the mxv ss pin is connected to board ground (v ss ). the mxv dd pin can be connected to the same 1.8-v power supply as dv ddr2 . figure 6-10. 1.8-v lvcmos-compatible clock input the clock source must meet the mxi/clkin timing requirements in section 6.7.4 , clock pll electrical data/timing (input and output clocks). submit documentation feedback peripheral information and electrical specifications 175 mxi/clkin mxo nc mxv ss 1.8 v mxv dd
6.7 clock plls 6.7.1 pll1 and pll2 tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com there are two independently controlled plls on dm6433. pll1 generates the frequencies required for the dsp, dma, and other peripherals. pll2 generates the frequencies required for the ddr2 interface and the vpbe in certain modes. the recommended reference clock for both plls is the 27-mhz crystal input. both pll1 and pll2 power is supplied externally via the 1.8 v pll power-supply pin (pll pwr18 ). an external emi filter circuit must be added to pll pwr18 , as shown in figure 6-11 . the 1.8-v supply of the emi filter must be from the same 1.8-v power plane supplying the device?s 1.8-v i/o power-supply pins (dv dddr2 ). ti recommends emi filter manufacturer murata, part number nfm18cc222r1c3. all pll external components (c1, c2, and the emi filter) must be placed as close to the device as possible. for the best performance, ti recommends that all the pll external components be on a single side of the board without jumpers, switches, or components other than the ones shown in figure 6-11 . for reduced pll jitter, maximize the spacing between switching signals and the pll external components (c1, c2, and the emi filter). figure 6-11. pll1 and pll2 external connection the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 6.7.4 , clock pll electrical data/timing (input and output clocks). there is an allowable range for pll multiplier (pllm). there is a minimum and maximum operating frequency for mxi/clkin, pllout, and the device clocks (sysclks). the pll controllers must be configured not to exceed any of these constraints documented in this section (certain combinations of external clock inputs, internal dividers, and pll multiply ratios might not be supported). for these constraints (ranges), see table 6-14 through table 6-16 . table 6-14. pll1 and pll2 multiplier ranges pll multiplier (pllm) min max pll1 multiplier x14 x30 pll2 multiplier x14 x32 peripheral information and electrical specifications 176 submit documentation feedback pll pwr18 c2 c1 emi filter +1.8 v 0.01 f dm643x pll2 pll1 0.1 f
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-15. pllc1 clock frequency ranges clock signal name min max unit mxi/clkin (1) 20 30 mhz -7 devices 300 700 mhz pllout cv dd = 1.2 v -6/-5/-4/-l/-q6/-q5/-q4 devices 300 600 mhz -7 devices 300 520 mhz pllout cv dd = 1.05 v -6/-5/-4/-l/-q5 devices 300 520 mhz -7 devices 700 mhz -q6 devices 660 mhz sysclk1 (2) (clkdiv1 domain) -6/-l devices 600 mhz cv dd = 1.2 v -5/-q5 devices 500 mhz -4/-q4 devices 400 mhz -7 devices 520 mhz -6/-l devices 450 mhz sysclk1 (2) (clkdiv1 domain), cv dd = 1.05 v -5/-q5 devices 400 mhz -4 devices 350 mhz (1) mxi/clkin input clock is used for both pll controllers (pllc1 and pllc2). (2) applies to "tape and reel" part number counterparts as well. for more information, see section 2.8 , device and development-support tool nomenclature. table 6-16. pllc2 clock frequency ranges clock signal name min max unit mxi/clkin (1) 20 30 mhz at 1.2-v cv dd 300 900 mhz pllout at 1.05-v cv dd 300 666 mhz pll2_sysclk1 (to ddr2 phy) 333 mhz (1) mxi/clkin input clock is used for both pll controllers (pllc1 and pllc2). both pll1 and pll2 have stabilization, lock, and reset timing requirements that must be followed. the pll stabilization time is the amount of time that must be allotted for the internal pll regulators to become stable after the pll is powered up (after pllctl.pllpwrdn bit goes through a 1-to-0 transition). the pll should not be operated until this stabilization time has expired. this stabilization step must be applied after these resets?a power-on reset, a warm reset, or a max reset, as the pllctl.pllpwrdn bit resets to a "1". for the pll stabliziation time value, see table 6-17 . the pll reset time is the amount of wait time needed for the pll to properly reset (writing pllrst = 0) before bringing the pll out of reset (writing pllrst = 1). for the pll reset time value, see table 6-17 . the pll lock time is the amount of time needed from when the pll is taken out of reset (pllrst = 1 with pllen = 0) to when to when the pll controller can be switched to pll mode (pllen = 1). for the pll lock time value, see table 6-17 . table 6-17. pll1 and pll2 stabilization, lock, and reset times pll stabilization/lock/reset min typ max unit time pll stabilization time 150 m s pll lock time 2000c (1) ns pll reset time 128c (1) ns (1) c = clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use c = 37. 037 ns. submit documentation feedback peripheral information and electrical specifications 177
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com for details on the pll initialization software sequence, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). for more information on the clock domains and their clock ratio restrictions, see section 6.3.4 , dm6433 power and clock domains. 178 peripheral information and electrical specifications submit documentation feedback
6.7.2 pll controller register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 a summary of the pll controller registers is shown in table 6-18 . for more details, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). table 6-18. pll and reset controller registers memory map hex address range register acronym description pll1 controller registers 0x01c4 0800 pid peripheral id register 0x01c4 08e4 rstype reset type register 0x01c4 0900 pllctl pll controller 1 pll control register 0x01c4 0910 pllm pll controller 1 pll multiplier control register 0x01c4 0918 plldiv1 pll controller 1 divider 1 register (sysclk1) 0x01c4 091c plldiv2 pll controller 1 divider 2 register (sysclk2) 0x01c4 0920 plldiv3 pll controller 1 divider 3 register (sysclk3) 0x01c4 0924 oscdiv1 pll controller 1 oscillator divider 1 register (obsclk) [clkout0 pin] 0x01c4 0928 ? reserved 0x01c4 092c bpdiv pll controller 1 bypass divider register (sysclkbp) 0x01c4 0938 pllcmd pll controller 1 command register 0x01c4 093c pllstat pll controller 1 status register (shows pllc1 status) pll controller 1 clock align control register 0x01c4 0940 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 1 plldiv divider ratio change status register 0x01c4 0944 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0948 cken pll controller 1 clock enable control register 0x01c4 094c ckstat pll controller 1 clock status register (for all clocks except sysclkx) 0x01c4 0950 systat pll controller 1 sysclk status register (indicates sysclk on/off status) 0x01c4 0960 ? reserved 0x01c4 0964 ? reserved pll2 controller registers 0x01c4 0c00 pid peripheral id register 0x01c4 0d00 pllctl pll controller 2 pll control register 0x01c4 0d10 pllm pll controller 2 pll multiplier control register 0x01c4 0d18 plldiv1 pll controller 2 divider 1 register (sysclk1) 0x01c4 0d1c plldiv2 pll controller 2 divider 2 register (sysclk2) 0x01c4 0d20 - 0x01c4 0d2c ? reserved 0x01c4 0d2c bpdiv pll controller 2 bypass divider register (sysclkbp) 0x01c4 0d38 pllcmd pll controller 2 command register 0x01c4 0d3c pllstat pll controller 2 status register (shows pllc2 status) pll controller 2 clock align control register 0x01c4 0d40 alnctl (indicates which sysclks need to be aligned for proper device operation) pll controller 2 plldiv divider ratio change status register 0x01c4 0d44 dchange (indicates if sysclk divide ratio has been modified) 0x01c4 0d48 ? reserved 0x01c4 0d4c ckstat pll controller 2 clock status register (for all clocks except sysclkx) 0x01c4 0d50 systat pll controller 2 sysclk status register (indicates sysclk on/off status) 0x01c4 0d54 - 0x01c4 0fff ? reserved submit documentation feedback peripheral information and electrical specifications 179
6.7.3 clock pll considerations with external clock sources tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com if the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power both the dm6433 device and the external clock oscillator circuit. the minimum clkin rise and fall times should also be observed. for the input clock timing requirements, see section 6.7.4 , clock pll electrical data/timing (input and output clocks). rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see section 5.3 , electrical characteristics over recommended ranges of supply voltage and operating temperature and section 6.7.4 , clock pll electrical data/timing (input and output clocks). 180 peripheral information and electrical specifications submit documentation feedback
6.7.4 clock pll electrical data/timing (input and output clocks) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-19. timing requirements for mxi/clkin (1) (2) (3) (4) (see figure 6-12 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t c(mxi) cycle time, mxi/clkin 33. 3 50 ns 2 t w(mxih) pulse duration, mxi/clkin high 0.45c 0.55c ns 3 t w(mxil) pulse duration, mxi/clkin low 0.45c 0.55c ns 4 t t(mxi) transition time, mxi/clkin 0.05c ns 5 t j(mxi) period jitter, mxi/clkin 0.02c ns frequency stability (5) 50 ppm (1) the mxi/clkin frequency and pll multiply factor should be chosen such that the resulting clock frequency is within the specific range for cpu operating frequency. for example, for a -6 speed device with a 27 mhz clkin frequency, the pll multiply factor should be 22. (2) the reference points for the rise and fall transitions are measured at v il max and v ih min. (3) for more details on the pll multiplier factors, see the tms320dm63x dmp dsp subsystem reference guide (literature number spru978 ). (4) c = clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use c = 37. 037 ns. (5) applies only when using the vpbe for ntsc or pal compliant video. for video and audio applications, stability of the input clock is very important. the user should select a clock with low enough ppm to ensure good video and audio quality for the specific application. if the vpbe is used for ntsc or pal compliant video output, ti recommends a 27-mhz, 50-ppm clock. for more details on this ntsc and pal compliant output video, see section 6.10.2 , video processing back-end (vpbe). figure 6-12. mxi/clkin timing table 6-20. switching characteristics over recommended operating conditions for clkout0 (1) (2) (see figure 6-13 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 1 t c cycle time, clkout0 33.3 50 ns 2 t w(clkout0h) pulse duration, clkout0 high 0.45p 0.55p ns 3 t w(clkout0l) pulse duration, clkout0 low 0.45p 0.55p ns 4 t t(clkout0) transition time, clkout0 0.05p ns (1) the reference points for the rise and fall transitions are measured at v ol max and v oh min. (2) p = 1/clkout0 clock frequency in nanoseconds (ns). for example, when clkout0 frequency is 27 mhz, use p = 37.04 ns. figure 6-13. clkout0 timing submit documentation feedback peripheral information and electrical specifications 181 mxi/clkin 2 3 4 4 5 1 clk_out0 (divide-by-1) 4 4 2 1 3
6.8 interrupts tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the c64x+ dsp interrupt controller combines device events into 12 prioritized interrupts. the source for each of the 12 cpu interrupts is user programmable and is listed in table 6-21 . also, the interrupt controller controls the generation of the cpu exception and emulation interrupts. the nmi input to the c64x+ dsp interrupt controller is not connected internally; therefore, the nmi interrupt is not available. table 6-22 summarizes the c64x+ interrupt controller registers and memory locations. for more details on dsp interrupt controller, see the tms320dm643x dmp dsp subsystem reference guide (literature number spru978 ). table 6-21. dm6433 dsp system event mapping dsp dsp system acronym source interrupt acronym source event number number 0 evt0 c64x+ int ctl 0 64 gpio0 gpio 1 evt1 c64x+ int ctl 1 65 gpio1 gpio 2 evt2 c64x+ int ctl 2 66 gpio2 gpio 3 evt3 c64x+ int ctl 3 67 gpio3 gpio 4 tintl0 timer 0 ? tint12 68 gpio4 gpio 5 tinth0 timer 0 ? tint34 69 gpio5 gpio 6 tintl1 timer 1 ? tint12 70 gpio6 gpio 7 tinth1 timer 1 ? tint34 71 gpio7 gpio 8 wdint timer 2 ? tint12 72 gpiobnk0 gpio 9 emu_dtdma c64x+ emc 73 gpiobnk1 gpio 10 reserved 74 gpiobnk2 gpio 11 emu_rtdxrx c64x+ rtdx 75 gpiobnk3 gpio 12 emu_rtdxtx c64x+ rtdx 76 gpiobnk4 gpio 13 idmaint0 c64x+ emc 0 77 gpiobnk5 gpio 14 idmaint1 c64x+ emc 1 78 gpiobnk6 gpio 15 reserved 79 reserved 16 reserved 80 pwm0 pwm0 17 reserved 81 pwm1 pwm1 18 reserved 82 pwm2 pwm2 19 reserved 83 iicint0 i2c 20 reserved 84 uartint0 uart0 21 reserved 85 reserved 22 reserved 86 reserved 23 reserved 87 reserved 24 reserved 88 reserved 25 reserved 89 reserved 26 reserved 90 reserved 27 reserved 91 reserved 28 reserved 92 reserved 29 reserved 93 reserved 30 rszint vpss ? resizer 94 reserved 31 reserved 95 reserved vencint vpss ? vpbe (venc) interr c64x+ interrupt controller dropped cpu 32 96 interrupt event 33 reserved 97 emc_idmaerr c64x+ emc invalid idma parameters 34 edma3cc_intg edmacc global interupt 98 reserved 35 edma3cc_int0 edmacc interrupt region 0 99 reserved 36 edma3cc_int1 edmacc interrupt region 1 100 reserved 37 edma3cc_errint edma cc error 101 reserved 38 edma3tc_errint0 edma tc0 error 102 reserved 39 edma3tc_errint1 edma tc1 error 103 reserved 40 edma3tc_errint2 edma tc2 error 104 reserved 41 pscint psc allint 105 reserved 42 reserved 106 reserved peripheral information and electrical specifications 182 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-21. dm6433 dsp system event mapping (continued) dsp dsp system acronym source interrupt acronym source event number number 43 emacint emac memory controller 107 reserved 44 reserved 108 reserved 45 reserved 109 reserved 46 reserved 110 reserved 47 hpiint hpi 111 reserved 48 mbxint0 mcbsp0 transmit 112 reserved 49 mbrint0 mcbsp0 receive 113 pmc_ed c64x+ pmc 50 reserved 114 reserved 51 reserved 115 reserved 52 reserved 116 umced1 c64x+ umc 1 53 ddrint ddr2 memory controller 117 umced2 c64x+ umc 2 54 emifaint emifa 118 pdcint c64x+ pdc 55 vlqint vlynq 119 syscmpa c64x+ sys 56 pciint pci 120 pmccmpa c64x+ pmc 57 reserved 121 pmcdmpa c64x+ pmc 58 reserved 122 dmccmpa c64x+ dmc 59 axint0 mcasp0 transmit 123 dmcdmpa c64x+ dmc 60 arint0 mcasp0 receive 124 umccmpa c64x+ umc 61 reserved 125 umcdmpa c64x+ umc 62 reserved 126 emccmpa c64x+ emc 63 reserved 127 emcbuserr c64x+ emc submit documentation feedback peripheral information and electrical specifications 183
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-22. c64x+ interrupt controller registers hex address acronym register description 0x0180 0000 evtflag0 event flag register 0 0x0180 0004 evtflag1 event flag register 1 0x0180 0008 evtflag2 event flag register 2 0x0180 000c evtflag3 event flag register 3 0x0180 0020 evtset0 event set register 0 0x0180 0024 evtset1 event set register 1 0x0180 0028 evtset2 event set register 2 0x0180 002c evtset3 event set register 3 0x0180 0040 evtclr0 event clear register 0 0x0180 0044 evtclr1 event clear register 1 0x0180 0048 evtclr2 event clear register 2 0x0180 004c evtclr3 event clear register 3 0x0180 0080 evtmask0 event mask register 0 0x0180 0084 evtmask1 event mask register 1 0x0180 0088 evtmask2 event mask register 2 0x0180 008c evtmask3 event mask register 3 0x0180 00a0 mevtflag0 masked event flag register 0 0x0180 00a4 mevtflag1 masked event flag register 1 0x0180 00a8 mevtflag2 masked event flag register 2 0x0180 00ac mevtflag3 masked event flag register 3 0x0180 00c0 expmask0 exception mask register 0 0x0180 00c4 expmask1 exception mask register 1 0x0180 00c8 expmask2 exception mask register 2 0x0180 00cc expmask3 exception mask register 3 0x0180 00e0 mexpflag0 masked exception flag register 0 0x0180 00e4 mexpflag1 masked exception flag register 1 0x0180 00e8 mexpflag2 masked exception flag register 2 0x0180 00ec mexpflag3 masked exception flag register 3 0x0180 0104 intmux1 interrupt mux register 1 0x0180 0108 intmux2 interrupt mux register 2 0x0180 010c intmux3 interrupt mux register 3 0x0180 0180 intxstat interrupt exception status 0x0180 0184 intxclr interrupt exception clear 0x0180 0188 intdmask dropped interrupt mask register peripheral information and electrical specifications 184 submit documentation feedback
6.9 external memory interface (emif) 6.9.1 asynchronous emif (emifa) 6.9.2 nand (nand, smartmedia, xd) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 dm6433 supports several memory and external device interfaces, including: asynchronous emif (emifa) for interfacing to nor flash, sram, etc. nand flash the dm6433 asynchronous emif (emifa) provides an 8-bit data bus, an address bus width up to 24-bits, and 4 chip selects, along with memory control signals. these signals are multiplexed between these peripherals: emifa and nand interfaces vpbe (venc) pci gpio the emifa interface provides both the asynchronous emif and nand interfaces. four chip selects are provided and each are individually configurable to provide either emifa or nand support. the nand features supported are as follows. nand flash on up to 4 asynchronous chip selects. 8-bit data bus width programmable cycle timings. performs ecc calculation. nand mode also supports smartmedia and xd memory cards boot rom supports booting of the dm6433 from nand flash located at cs2 the memory map for emifa and nand registers is shown in table 6-23 . for more details on the emifa and nand interfaces, see section 2.9 , documentation support for the link to the tms320dm643x dmp peripherals overview reference guide (literature number spru983) for the tms320dm643x asynchronous external memory interface (emif) user's guide (literature number spru984). submit documentation feedback peripheral information and electrical specifications 185
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-23. emifa/nand registers hex address range acronym register name 0x01e0 0000 rcsr revision code and status register 0x01e0 0004 awccr asynchronous wait cycle configuration register 0x01e0 0008 - 0x01e0 000f - reserved 0x01e0 0010 a1cr asynchronous 1 configuration register (cs2 space) 0x01e0 0014 a2cr asynchronous 2 configuration register (cs3 space) 0x01e0 0018 a3cr asynchronous 3 configuration register (cs4 space) 0x01e0 001c a4cr asynchronous 4 configuration register (cs5 space) 0x01e0 0020 - 0x01e0 003f - reserved 0x01e0 0040 eirr emif interrupt raw register 0x01e0 0044 eimr emif interrupt mask register 0x01e0 0048 eimsr emif interrupt mask set register 0x01e0 004c eimcr emif interrupt mask clear register 0x01e0 0050 - 0x01e0 005f - reserved 0x01e0 0060 nandfcr nand flash control register 0x01e0 0064 nandfsr nand flash status register 0x01e0 0070 nandf1ecc nand flash 1 ecc register (cs2 space) 0x01e0 0074 nandf2ecc nand flash 2 ecc register (cs3 space) 0x01e0 0078 nandf3ecc nand flash 3 ecc register (cs4 space) 0x01e0 007c nandf4ecc nand flash 4 ecc register (cs5 space) 0x01e0 0080 - 0x01e0 0fff - reserved peripheral information and electrical specifications 186 submit documentation feedback
6.9.3 emifa electrical data/timing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-24. timing requirements for asynchronous memory cycles for emifa module (1) (see figure 6-14 and figure 6-15 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min nom max reads and writes 2 t w(em_wait) pulse duration, em_wait assertion and deassertion 2e ns reads 12 t su(emdv-emoeh) setup time, em_d[7:0] valid before em_oe high 5 ns 13 t h(emoeh-emdiv) hold time, em_d[7:0] valid after em_oe high 0 ns t su(emwait- 14 setup time, em_wait asserted before em_oe high (2) 4e + 5 ns emoeh) writes t su(emwait- 28 setup time, em_wait asserted before em_we high (2) 4e + 5 ns emweh) (1) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 600 mhz, use e = 10 ns. (2) setup before end of strobe phase (if no extended wait states are inserted) by which em_wait must be asserted to add extended wait states. figure 6-16 and figure 6-17 describe emif transactions that include extended wait states inserted during the strobe phase. however, cycles inserted as part of this extended wait period should not be counted; the 4e requirement is to the start of where the hold phase would begin if there were no extended wait cycles. submit documentation feedback peripheral information and electrical specifications 187
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-25. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (1) (2) (see figure 6-14 and figure 6-15 ) -7/-6/-5/-4 no -l/-q6/-q5/-q4 parameter unit . min nom max reads and writes 1 t d(turnaround) turn around time (ta + 1) * e ns reads (rs + rst + rh + 3 t c(emrcycle) emif read cycle time ns ta + 4) * e (3) output setup time, em_cs[5:2] low to (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low (ss = 0) 4 t su(emcsl-emoel) output setup time, em_cs[5:2] low to -4 4 ns em_oe low (ss = 1) output hold time, em_oe high to (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_cs[5:2] high (ss = 0) 5 t h(emoeh-emcsh) output hold time, em_oe high to -4 4 ns em_cs[5:2] high (ss = 1) output setup time, em_ba[1:0] valid to 6 t su(embav-emoel) (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low output hold time, em_oe high to 7 t h(emoeh-embaiv) (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_ba[1:0] invalid output setup time, em_a[21:0] valid to 8 t su(embav-emoel) (rs + 1) * e - 4 (rs + 1) * e + 4 ns em_oe low output hold time, em_oe high to 9 t h(emoeh-embaiv) (rh + 1) * e - 4 (rh + 1) * e + 4 ns em_a[21:0] invalid 10 t w(emoel) em_oe active low width (rst + 1) * e (3) ns delay time from em_wait deasserted 11 t d(emwaith-emoeh) 4e + 4 ns to em_oe high writes (ws + wst + wh + 15 t c(emwcycle) emif write cycle time ns ta + 4) * e (3) output setup time, em_cs[5:2] low to (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low (ss = 0) 16 t su(emcsl-emwel) output setup time, em_cs[5:2] low to -4 4 ns em_we low (ss = 1) output hold time, em_we high to (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_cs[5:2] high (ss = 0) 17 t h(emweh-emcsh) output hold time, em_we high to -4 4 ns em_cs[5:2] high (ss = 1) output setup time, em_r/ w valid to 18 t su(emrnw-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 19 t h(emweh-emrnw) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_r/ w invalid output setup time, em_ba[1:0] valid to 20 t su(embav-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 21 t h(emweh-embaiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_ba[1:0] invalid output setup time, em_a[21:0] valid to 22 t su(emav-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 23 t h(emweh-emaiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_a[21:0] invalid (1) rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold, ta = turn around, ew = extend wait mode, ss = select strobe mode. these parameters are programmed via the asynchronous n configuration and asynchronous wait cycle configuration registers. (2) e = sysclk3 period in ns for emifa. for example, when running the dsp cpu at 600 mhz, use e = 10 ns. (3) when ew = 1, the emif will extend the strobe period up to 4,096 additional cycles when the em_wait pin is asserted by the external device. peripheral information and electrical specifications 188 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-25. switching characteristics over recommended operating conditions for asynchronous memory cycles for emifa module (see figure 6-14 and figure 6-15 ) (continued) -7/-6/-5/-4 no -l/-q6/-q5/-q4 parameter unit . min nom max 24 t w(emwel) em_we active low width (wst + 1) * e (3) ns delay time from em_wait deasserted 25 t d(emwaith-emweh) 4e + 4 ns to em_we high output setup time, em_d[7:0] valid to 26 t su(emdv-emwel) (ws + 1) * e - 4 (ws + 1) * e + 4 ns em_we low output hold time, em_we high to 27 t h(emweh-emdiv) (wh + 1) * e - 4 (wh + 1) * e + 4 ns em_d[7:0] invalid figure 6-14. asynchronous memory read timing for emif submit documentation feedback peripheral information and electrical specifications 189 em_cs[5:2] em_ba[1:0] 13 12 em_a[21:0] em_oe em_d[7:0] em_we 10 59 7 48 6 3 1 em_r/w
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 6-15. asynchronous memory write timing for emif figure 6-16. em_wait read timing requirements 190 peripheral information and electrical specifications submit documentation feedback em_cs[5:2] em_ba[1:0] em_a[21:0] em_we em_d[7:0] em_oe em_r/w 15 1 1618 2022 24 17 19 21 23 26 27 em_cs[5:2] 11 asserted deasserted 2 2 em_ba[1:0] em_a[21:0] em_d[7:0] em_oe em_wait setup strobe extended due to em_wait strobe hold 14
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-17. em_wait write timing requirements submit documentation feedback peripheral information and electrical specifications 191 em_cs[5:2] 25 asserted deasserted 2 2 em_ba[1:0] em_a[21:0] em_d[7:0] em_we em_wait setup strobe extended due to em_wait strobe hold 28
6.9.4 ddr2 memory controller 6.9.4.1 ddr2 memory controller electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the ddr2 memory controller is a dedicated interface to ddr2 sdram. it supports jesd79d-2a standard compliant ddr2 sdram devices and can interface to either 16-bit or 32-bit ddr2 sdram devices. for details on the ddr2 memory controller, see the tms320dm643x dmp ddr2 memory controller user?s guide (literature number spru986 ). ddr2 sdram plays a key role in a davinci-based system. such a system is expected to require a significant amount of high-speed external memory for: numerous osd display buffers buffering for intermediate data while performing video decode functions storage of executable code for the dsp a memory map of the ddr2 memory controller registers is shown in table 6-26 . table 6-26. ddr2 memory controller registers hex address range acronym register name 0x01c4 004c ddrvtper ddr2 vtp enable register 0x01c4 2038 ddrvtpr ddr2 vtp register 0x2000 0000 - 0x2000 0003 - reserved 0x2000 0004 sdrstat sdram status register 0x2000 0008 sdbcr sdram bank configuration register 0x2000 000c sdrcr sdram refresh control register 0x2000 0010 sdtimr sdram timing register 0x2000 0014 sdtimr2 sdram timing register 2 0x2000 0020 pbbpr peripheral bus burst priority register 0x2000 0024 - 0x2000 00bf - reserved 0x2000 00c0 irr interrupt raw register 0x2000 00c4 imr interrupt masked register 0x2000 00c8 imsr interrupt mask set register 0x2000 00cc imcr interrupt mask clear register 0x2000 00d0 - 0x2000 00e3 - reserved 0x2000 00e4 ddrphycr ddr phy control register 0x2000 00e8 - 0x2000 00ef - reserved 0x2000 00f0 vtpiocr ddr vtp io control register 0x2000 00f4 - 0x2000 7fff - reserved the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ) specifies a complete ddr2 interface solution for the dm6433 as well as a list of compatible ddr2 devices. ti has performed the simulation and system characterization to ensure all ddr2 interface timings in this solution are met. ti only supports board designs that follow the guidelines outlined in the implementing ddr2 pcb layout on the tms320dm643x dmp dmsoc application report (literature number spraal6 ). 192 peripheral information and electrical specifications submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-27. switching characteristics over recommended operating conditions for ddr2 memory controller (1) (2) (see figure 6-18 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 1 t c(ddr_clk) cycle time, ddr_clk 6 8 ns (1) ddr_clk cycle time = 2 x pll2 _sysclk1 cycle time. (2) the pll2 controller must be programmed such that the resulting ddr_clk clock frequency is within the specified range. figure 6-18. ddr2 memory controller clock timing submit documentation feedback peripheral information and electrical specifications 193 ddr_clk 1
6.10 video processing sub-system (vpss) overview 6.10.1 video processing front-end (vpfe) 6.10.1.1 resizer tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dm6433 video processing sub-system (vpss) provides a video processing front end (vpfe) input interface for external imaging peripherals (resizer only) and a video processing back end (vpbe) output interface for display devices, such as analog sdtv displays, digital lcd panels, hdtv video encoders, etc. the vpss register memory mapping is shown in table 6-28 . table 6-28. vpss register descriptions hex address range register acronym description 0x01c7 3400 pid peripheral revision and class information 0x01c7 3404 pcr vpss control register 0x01c7 3408 - reserved 0x01c7 3508 sdr_reg_exp sdram non real-time read request expand 0x01c7 350c - - reserved 0x01c7 3fff the video processing front-end (vpfe) on the dm6433 consists of the resizer. the resizer module re-sizes the input image data to the desired display or video encoding resolution. the vpfe register memory mapping is shown in table 6-29 . table 6-29. vpfe register address range descriptions hex address range acronym register name 0x01c7 0400 ? 0x01c7 0bff reserved 0x01c7 0c00 ? 0x01c7 09ff resz vpfe ? resizer 0x01c7 1000 ? 0x01c7 17ff reserved 0x01c7 3400 ? 0x01c7 3fff vpss vpss shared buffer logic registers (see table 6-28 ) the resizer module can accept input image/video data from the ddr2. the output of the resizer module is sent to ddr2. the following features are supported by the resizer module. an output width up to 1280 horizontal pixels. input from external ddr2. up to 4x upsampling (digital zoom). bi-cubic interpolation (4-tap horizontal, 4-tap vertical) can be implemented with the programmable filter coefficients. 8 phases of filter coefficients. optional bi-linear interpolation for the chrominance components. up to 1/4x downsampling 4-tap horizontal and 4-tap vertical filter coefficients (with 8-phases) for 1x to 1/2x downsampling 1/2x to 1/4x downsampling, for 7-tap mode with 4-phases. resizing either yuv 4:2:2 packed data (16-bits) or color separate data (8-bit data within ddr) that is contiguous. separate/independent resizing factor for the horizontal and vertical directions. upsampling and downsampling ratios that are available are: 256/n, with n ranging from 64 to 1024. programmable luminance sharpening after the horizontal resizing and before the vertical resizing step. the resizer register memory mapping is shown in table 6-30 . peripheral information and electrical specifications 194 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-30. resizer register descriptions hex address range register acronym description 0x01c7 0c00 pid peripheral revision and class information 0x01c7 0c04 pcr peripheral control register 0x01c7 0c08 rsz_cnt resizer control bits the dm6433 device does not support preview engine on vpfe. note: for proper dm6433 device operation, the rsz_cnt.inpsrc bit field must be set to ddr2 memory controller (sdram). 0x01c7 0c0c out_size output width and height after resizing 0x01c7 0c10 in_start input starting information 0x01c7 0c14 in_size input width and height before resizing 0x01c7 0c18 sdr_inadd input sdram address 0x01c7 0c1c sdr_inoff sdram offset for the input line 0x01c7 0c20 sdr_outadd output sdram address 0x01c7 0c24 sdr_outoff sdram offset for the output line 0x01c7 0c28 hfilt10 horizontal filter coefficients 1 and 0 0x01c7 0c2c hfilt32 horizontal filter coefficients 3 and 2 0x01c7 0c30 hfilt54 horizontal filter coefficients 5 and 4 0x01c7 0c34 hfilt76 horizontal filter coefficients 7 and 6 0x01c7 0c38 hfilt98 horizontal filter coefficients 9 and 8 0x01c7 0c3c hfilt1110 horizontal filter coefficients 11 and 10 0x01c7 0c40 hfilt1312 horizontal filter coefficients 13 and 12 0x01c7 0c44 hfilt1514 horizontal filter coefficients 15 and 14 0x01c7 0c48 hfilt1716 horizontal filter coefficients 17 and 16 0x01c7 0c4c hfilt1918 horizontal filter coefficients 19 and 18 0x01c7 0c50 hfilt2120 horizontal filter coefficients 21 and 20 0x01c7 0c54 hfilt2322 horizontal filter coefficients 23 and 22 0x01c7 0c58 hfilt2524 horizontal filter coefficients 25 and 24 0x01c7 0c5c hfilt2726 horizontal filter coefficients 27 and 26 0x01c7 0c60 hfilt2928 horizontal filter coefficients 29 and 28 0x01c7 0c64 hfilt3130 horizontal filter coefficients 31 and 30 0x01c7 0c68 vfilt10 vertical filter coefficients 1 and 0 0x01c7 0c6c vfilt32 vertical filter coefficients 3 and 2 0x01c7 0c70 vfilt54 vertical filter coefficients 5 and 4 0x01c7 0c74 vfilt76 vertical filter coefficients 7 and 6 0x01c7 0c78 vfilt98 vertical filter coefficients 9 and 8 0x01c7 0c7c vfilt1110 vertical filter coefficients 11 and 10 0x01c7 0c80 vfilt1312 vertical filter coefficients 13 and 12 0x01c7 0c84 vfilt1514 vertical filter coefficients 15 and 14 0x01c7 0c88 vfilt1716 vertical filter coefficients 17 and 16 0x01c7 0c8c vfilt1918 vertical filter coefficients 19 and 18 0x01c7 0c90 vfilt2120 vertical filter coefficients 21 and 20 0x01c7 0c94 vfilt2322 vertical filter coefficients 23 and 22 0x01c7 0c98 vfilt2524 vertical filter coefficients 25 and 24 0x01c7 0c9c vfilt2726 vertical filter coefficients 27 and 26 0x01c7 0ca0 vfilt2928 vertical filter coefficients 29 and 28 0x01c7 0ca4 vfilt3130 vertical filter coefficients 31 and 30 0x01c7 0ca8 yenh luminance enhancer submit documentation feedback peripheral information and electrical specifications 195
6.10.2 video processing back-end (vpbe) 6.10.2.1 on-screen display (osd) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the video processing back-end (vpbe) consists of the on-screen display (osd) module, the video encoder (venc) including the digital lcd (dlcd) and analog (i.e., dac) interfaces. the video encoder generates analog video output. the dlcd controller generates digital rgb/ycbcr data output and timing signals. the vpbe register memory mapping is shown in table 6-31 . table 6-31. vpbe register descriptions address register description 0x01c7 2780 pid peripheral revision and class information register 0x01c7 2784 pcr peripheral control register to ensure ntsc and pal compliant output video, the stability of the input clock source is very important. ti recommends a 27-mhz, 50-ppm crystal. ceramic oscillators are not recommended. the ntsc/pal color sub-carrier frequency is derived from the 27-mhz clock; therefore, if the 27-mhz clock drifts, then the color sub-carrier frequency will drift as well. assuming no 27-mhz frequency drift, the color sub-carrier frequency is generated as follows: to ensure the color sub-carrier frequency will not drift out of specification, the user must follow the crystal requirements discussed in section 6.6.1 , clock input option 1?crystal. alternatively, if the vpbe input clock is sourced from the vpbeclk, this clock must have a frequency stability of 50 ppm to ensure ntsc and pal compliant output video. the major function of the osd module is to gather and blend video data and display/bitmap data before feeding it to the video encoder (venc) in ycbcr format. the video and display data is read from an external memory, typically ddr2. the osd is programmed via control and parameter registers. the following are the primary features that are supported by the osd. simultaneous display of two video windows and two osd windows (vidwin0/vidwin1 and osdwin0/osdwin1). ? separate enable for each window ? programmable width, height, and base starting coordinates for each window ? external memory address and offset registers for each window ? support for x2 and x4 zoom in both the horizontal and vertical direction ? osdwin1 can be used as an attribute window for osdwin0 ? attribute window blinking intervals ? field/frame mode for the windows (interlaced/progressive) ? eight step blending process between the osd and video windows ? transparency support for the osd and video data (when a bitmap pixel is zero, there will be no blending for that corresponding video pixel) ? resize from vga to ntsc/pal (640x480 to 720x576) for both the osd and video windows ? reads in ycbcr data in 4:2:2 format from external memory, with the capability for swapping the order of the cbcr component in the 32-bit word (this is relevant to the two video windows) ? support for a ping-pong buffer scheme that can be used for vidwin0 (allows for video data to be accessed from two different locations in ddr2) ? each osd window (either one, but not both at the same time) is capable of reading in rgb data peripheral information and electrical specifications 196 submit documentation feedback f sc-ntsc 35 = 27 mhz = 3.5795454545 mhz 264 ? ? ? ? 167 f = 27 mhz = 4.4332628318 mhz sc- pal 1017 ? ? ? ?
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 (16-bit data with six bits for the green and five bits each for the red and blue colors) instead of bitmap data in ycbcr format restricted to a maximum of 8-bits ? the osd bitmap data width is selectable between 1, 2, 4, or 8-bits. ? each osd window supports 16 entries for the bitmap (to index into a 256 entry ram/rom clut table). ? indirect support for 24-bit rgb input data (which will be transformed into 16-bit ycbcr video window data) via the wrapper interface in the vpbe. support for a rectangular cursor window and a programmable background color selection. ? programmable color palette with the ability to select between a ram/rom table with support for 256 colors. ? the width, height, and color of the cursor is programmable. ? the display priority is: rectangular-cursor > osdwin1 > osdwin0 > vidwin1 > vidwin0 > background color support for attenuation of the ycbcr values for the rec601 standard. the following restrictions exist in the osd module. both the osd windows and vidwin1 should be fully contained inside vidwin0. when one of the osd windows is set in rgb mode, it cannot overlap with vidwin1. the osd cannot support more than 256 color entries in the clut ram/rom. some applications require higher number of entries, and one workaround is to use vidwin1 as an overlay mimicking the osd window. another option is to use the rgb mode for one of the osd windows which allows for a total of 16-bits for the r, g, and b colors (64k colors). the osd can only read ycbcr in 4:2:2 interleaved format for the video windows. other formats, either color separate storage or 4:4:4/4:2:0 interleaved data is not supported. if the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 720 currently. it is not possible to use both of the clut roms at the same time. however, one window can use ram while another uses rom. the 24-bit rgb input mode is only valid for one of the two video windows (programmable) and does not apply to the osd windows. the osd register memory mapping is shown in table 6-32 . table 6-32. osd register descriptions address register description 0x01c7 2600 mode osd mode register 0x01c7 2604 vidwinmd video window mode setup 0x01c7 2608 osdwin0md osd window mode setup 0x01c7 260c osdwin1md osd window 1 mode setup (when used as a second osd window) 0x01c7 260c osdatrmd osd attribute window mode setup (when used as an attribute window) 0x01c7 2610 rectcur rectangular cursor setup 0x01c7 2614 rsv0 reserved 0x01c7 2618 vidwin0ofst video window 0 offset 0x01c7 261c vidwin1ofst video window 1 offset 0x01c7 2620 osdwin0ofst osd window 0 offset 0x01c7 2624 osdwin1ofst osd window 1 offset 0x01c7 2628 rsv1 reserved 0x01c7 262c vidwin0adr video window 0 address 0x01c7 2630 vidwin1adr video window 1 address 0x01c7 2634 rsv2 reserved submit documentation feedback peripheral information and electrical specifications 197
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-32. osd register descriptions (continued) 0x01c7 2638 osdwin0adr osd window 0 address 0x01c7 263c osdwin1adr osd window 1 address 0x01c7 2640 basepx base pixel x 0x01c7 2644 basepy base pixel y 0x01c7 2648 vidwin0xp video window 0 x-position 0x01c7 264c vidwin0yp video window 0 y-position 0x01c7 2650 vidwin0xl video window 0 x-size 0x01c7 2654 vidwin0yl video window 0 y-size 0x01c7 2658 vidwin1xp video window 1 x-position 0x01c7 265c vidwin1yp video window 1 y-position 0x01c7 2660 vidwin1xl video window 1 x-size 0x01c7 2664 vidwin1yl video window 1 y-size 0x01c7 2668 osdwin0xp osd bitmap window 0 x-position 0x01c7 266c osdwin0yp osd bitmap window 0 y-position 0x01c7 2670 osdwin0xl osd bitmap window 0 x-size 0x01c7 2674 osdwin0yl osd bitmap window 0 y-size 0x01c7 2678 osdwin1xp osd bitmap window 1 x-position 0x01c7 267c osdwin1yp osd bitmap window 1 y-position 0x01c7 2680 osdwin1xl osd bitmap window 1 x-size 0x01c7 2684 osdwin1yl osd bitmap window 1 y-size 0x01c7 2688 curxp rectangular cursor window x-position 0x01c7 268c curyp rectangular cursor window y-position 0x01c7 2690 curxl rectangular cursor window x-size 0x01c7 2694 curyl rectangular cursor window y-size 0x01c7 2698 rsv3 reserved 0x01c7 269c rsv4 reserved 0x01c7 26a0 w0bmp01 window 0 bitmap value to palette map 0/1 0x01c7 26a4 w0bmp23 window 0 bitmap value to palette map 2/3 0x01c7 26a8 w0bmp45 window 0 bitmap value to palette map 4/5 0x01c7 26ac w0bmp67 window 0 bitmap value to palette map 6/7 0x01c7 26b0 w0bmp89 window 0 bitmap value to palette map 8/9 0x01c7 26b4 w0bmpab window 0 bitmap value to palette map a/b 0x01c7 26b8 w0bmpcd window 0 bitmap value to palette map c/d 0x01c7 26bc w0bmpef window 0 bitmap value to palette map e/f 0x01c7 26c0 w1bmp01 window 1 bitmap value to palette map 0/1 0x01c7 26c4 w1bmp23 window 1 bitmap value to palette map 2/3 0x01c7 26c8 w1bmp45 window 1 bitmap value to palette map 4/5 0x01c7 26cc w1bmp67 window 1 bitmap value to palette map 6/7 0x01c7 26d0 w1bmp89 window 1 bitmap value to palette map 8/9 0x01c7 26d4 w1bmpab window 1 bitmap value to palette map a/b 0x01c7 26d8 w1bmpcd window 1 bitmap value to palette map c/d 0x01c7 26dc w1bmpef window 1 bitmap value to palette map e/f 0x01c7 26e0 - reserved 0x01c7 26e4 rsv5 reserved 0x01c7 26e8 miscctl miscellaneous control 0x01c7 26ec clutramycb clut ramycb setup 0x01c7 26f0 clutramcr clut ram setup 0x01c7 26f4 transpval clut ram setup peripheral information and electrical specifications 198 submit documentation feedback
6.10.2.2 video encoder (venc) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-32. osd register descriptions (continued) 0x01c7 26f8 rsv6 reserved 0x01c7 26fc ppvwin0adr ping-pong video window 0 address analog/dacs interface of the video encoder (venc) supports the following features. master clock input - 27mhz (x2 upsampling) sdtv support ? composite ntsc-m, pal-b/d/g/h/i ? s-video (y/c) ? component ypbpr (smpte/ebu n10, betacam, mii) ? rgb ? non-interlace ? cgms/wss ? line 21 closed caption data encoding ? chroma low pass filter 1.5mhz/3mhz ? programmable sc-h phase hdtv support ? progressive output (525p/625p) ? component ypbpr ? rgb ? cgms/wss 4 10-bit over-sampling d/a converters optional 7.5% pedestal 16-235/0-255 input amplitude selectable programmable luma delay master/slave operation internal color bar generation (100%/75%) the digital lcd controller (dlcd) of the venc supports the following features. programmable dclk various output formats ? ycbcr 16bit ? ycbcr 8bit ? itu-r bt. 656 ? parallel rgb 24bit low pass filter for digital rgb output programmable timing generator master/slave operation internal color bar generation (100%/75%) the venc register memory mapping including the digital lcd and dacs is shown in table 6-33 . table 6-33. venc (including digital lcd and dacs) register descriptions address register description 0x01c7 2400 vmod video mode 0x01c7 2404 vidctl video interface i/o control 0x01c7 2408 vdpro video data processing submit documentation feedback peripheral information and electrical specifications 199
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-33. venc (including digital lcd and dacs) register descriptions (continued) 0x01c7 240c syncctl sync control 0x01c7 2410 hspls horizontal sync pulse width 0x01c7 2414 vspls vertical sync pulse width 0x01c7 2418 hint horizontal interval 0x01c7 241c hstart horizontal valid data start position 0x01c7 2420 hvalid horizontal data valid range 0x01c7 2424 vint vertical interval 0x01c7 2428 vstart vertical valid data start position 0x01c7 242c vvalid vertical data valid range 0x01c7 2430 hsdly horizontal sync delay 0x01c7 2434 vsdly vertical sync delay 0x01c7 2438 ycctl ycbcr control 0x01c7 243c rgbctl rgb control 0x01c7 2440 rgbclp rgb level clipping 0x01c7 2444 linectl line id control 0x01c7 2448 cullline culling line control 0x01c7 244c lcdout lcd output signal control 0x01c7 2450 brts brightness start position signal control 0x01c7 2454 brtw brightness width signal control 0x01c7 2458 acctl lcd_ac signal control 0x01c7 245c pwmp pwm start position signal control 0x01c7 2460 pwmw pwm width signal control 0x01c7 2464 dclkctl dclk control 0x01c7 2468 dclkptn0 dclk pattern 0 0x01c7 246c dclkptn1 dclk pattern 1 0x01c7 2470 dclkptn2 dclk pattern 2 0x01c7 2474 dclkptn3 dclk pattern 3 0x01c7 2478 dclkptn0a dclk auxiliary pattern 0 0x01c7 247c dclkptn1a dclk auxiliary pattern 1 0x01c7 2480 dclkptn2a dclk auxiliary pattern 2 0x01c7 2484 dclkptn3a dclk auxiliary pattern 3 0x01c7 2488 dclkhs horizontal dclk mask start 0x01c7 248c dclkhsa horizontal auxiliary dclk mask start 0x01c7 2490 dclkhr horizontal dclk mask range 0x01c7 2494 dclkvs vertical dclk mask start 0x01c7 2498 dclkvr vertical dclk mask range 0x01c7 249c capctl caption control 0x01c7 24a0 capdo caption data odd field 0x01c7 24a4 capde caption data even field 0x01c7 24a8 atr0 video attribute data # 0 0x01c7 24ac atr1 video attribute data # 1 0x01c7 24b0 atr2 video attribute data # 2 0x01c7 24b4 0x01c7 24b4 reserved 0x01c7 24b4 0x01c7 24b4 0x01c7 24b8 vstat video status peripheral information and electrical specifications 200 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-33. venc (including digital lcd and dacs) register descriptions (continued) 0x01c7 24bc reserved 0x01c7 24c0 0x01c7 24c4 dactst dac test 0x01c7 24c8 ycolvl yout and cout levels 0x01c7 24cc scprog sub-carrier programming 0x01c7 24d0 0x01c7 24d4 reserved 0x01c7 24d8 0x01c7 24dc cvbs composite mode 0x01c7 24e0 cmpnt component mode 0x01c7 24e4 etmg0 cvbs timing control 0 0x01c7 24e8 etmg1 cvbs timing control 1 0x01c7 24ec etmg2 component timing control 0 0x01c7 24f0 etmg3 component timing control 1 0x01c7 24f4 dacsel dac output select 0x01c7 24f8 reserved 0x01c7 24fc 0x01c7 2500 argbx0 analog rgb matrix 0 0x01c7 2504 argbx1 analog rgb matrix 1 0x01c7 2508 argbx2 analog rgb matrix 2 0x01c7 250c argbx3 analog rgb matrix 3 0x01c7 2510 argbx4 analog rgb matrix 4 0x01c7 2514 drgbx0 digital rgb matrix 0 0x01c7 2518 drgbx1 digital rgb matrix 1 0x01c7 251c drgbx2 digital rgb matrix 2 0x01c7 2520 drgbx3 digital rgb matrix 3 0x01c7 2524 drgbx4 digital rgb matrix 4 0x01c7 2528 vstarta vertical data valid start position for even field 0x01c7 252c osdclk0 osd clock control 0 0x01c7 2530 osdclk1 osd clock control 1 0x01c7 2534 hvldcl0 horizontal valid culling control 0 0x01c7 2538 hvldcl1 horizontal valid culling control 1 0x01c7 253c osdhadv osd horizontal sync advance submit documentation feedback peripheral information and electrical specifications 201
6.10.3 vpbe electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-34. timing requirements for vpbe clk input (1) (see figure 6-19 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t c(vpbeclk) cycle time, vpbeclk 13.33 ns 2 t w(vpbeclkh) pulse duration, vpbeclk high .4v ns 3 t w(vpbeclkl) pulse duration, vpbeclk low .4v ns 4 t t(vpbeclk) transition time, vpbeclk 7 ns (1) v = vpbeclk period in ns. figure 6-19. vpbeclk timing peripheral information and electrical specifications 202 submit documentation feedback 3 1 2 4 vpbeclk 4
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-35. timing requirements for vpbe control input with respect to vpbeclk (see figure 6-20 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 27 t su(vctlv-vpbeclk) setup time, vctl valid before vpbeclk rising edge 3 ns 28 t h(vpbeclk-vctlv) hold time, vctl valid after vpbeclk rising edge 1 ns 35 t su(field-vpbeclk) setup time, lcd_field valid before vpbeclk rising edge 5p (1) ns 36 t h(vpbeclk-field) hold time, lcd_field valid after vpbeclk rising edge 5p (1) ns (1) p = 1/(vpbeclk clock frequency) in ns. figure 6-20. vpbe input timing with respect to vpbeclk submit documentation feedback peripheral information and electrical specifications 203 vctl (a) a. vctl = hsync and vsync vpbeclk 27 28 35 36 lcd_field
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-36. switching characteristics over recommended operating conditions for vpbe control and data output with respect to vpbeclk (see figure 6-21 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 29 t d(vpbeclk-vctlv) delay time, vpbeclk rising edge to vctl valid 14 ns 30 t d(vpbeclk-vctliv) delay time, vpbeclk rising edge to vctl invalid 2.5 ns 31 t d(vpbeclk-vdatav) delay time, vpbeclk rising edge to vdata valid 14 ns 32 t d(vpbeclk-vdataiv) delay time, vpbeclk rising edge to vdata invalid 2.5 ns figure 6-21. vpbe output timing with respect to vpbeclk 204 peripheral information and electrical specifications submit documentation feedback 31 29 vctl (a) a. vctl = hsync, vsync, lcd_field, and lcd_oe b. vdat a = cout[7:0], yout[7:0], r[7:0], g[7:0], and b[7:0] vdata (b) 32 30 vpbeclk
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-37. switching characteristics over recommended operating conditions for vpbe control and data output with respect to vclk (1) (2) (3) (see figure 6-22 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 17 t c(vclk) cycle time, vclk 13.33 160 ns 18 t w(vclkh) pulse duration, vclk high 0.4c ns 19 t w(vclkl) pulse duration, vclk low 0.4c ns 20 t t(vclk) transition time, vclk 7 ns 21 t d(vclkinh-vclkh) delay time, vclkin high to vclk high 1 9 ns 22 t d(vclkinl-vclkl) delay time, vclkin low to vclk low 1 9 ns 23 t d(vclk-vctlv) delay time, vclk edge to vctl valid 9 ns 24 t d(vclk-vctliv) delay time, vclk edge to vctl invalid 0.6 ns 25 t d(vclk-vdatav) delay time, vclk edge to vdata valid 9 ns 26 t d(vclk-vdataiv) delay time, vclk edge to vdata invalid 0.6 ns (1) the vpbe may be configured to operate in either positive or negative edge clocking mode. when in positive edge clocking mode, the rising edge of vclk is referenced. when in negative edge clocking mode, the falling edge of vclk is referenced. (2) vclkin = vpbeclk (3) c = vclk period in ns. figure 6-22. vpbe control and data output timing with respect to vclk submit documentation feedback peripheral information and electrical specifications 205 vclk (positive edge clocking) vclk (negative edge clocking) 17 vctl (b) vdata (c) 18 19 22 21 23 24 25 26 vclkin (a) a. vclkin = vpbeclk b. vctl = hsync, vsync, lcd_field, and lcd_oe c. vdat a = cout[7:0], yout[7:0], r[7:0], g[7:0], and b[7:0] 20 20
6.10.3.1 dac electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-38. switching characteristics over recommended operating conditions for dac static specifications -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter test conditions unit min typ max dc accuracy -1.0 1.0 lsb integral non-linearity (inl) -0.5 0.5 lsb differential non-linearity (dnl) analog output 0.5 lsb offset error 5 %f s gain error 500 mv pp full-scale output voltage r load = 500 peripheral information and electrical specifications 206 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the dm6433's analog video dac outputs are designed to drive a 500- submit documentation feedback peripheral information and electrical specifications 207 lowpassfilter =6.5mhz ~r =500 f c load dac 75 75 i out amplifier gain=5.6v/v
6.11 universal asynchronous receiver/transmitter (uart) 6.11.1 uart peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dm6433 device has one uart peripheral (uart0). uart0 has the following features: 16-byte storage space for both the transmitter and receiver fifos 1, 4, 8, or 14 byte selectable receiver fifo trigger level for autoflow control and dma dma signaling capability for both received and transmitted data programmable auto-rts and auto-cts for autoflow control frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates prioritized interrupts programmable serial data formats ? 5, 6, 7, or 8-bit characters ? even, odd, or no parity bit generation and detection ? 1, 1.5, or 2 stop bit generation false start bit detection line break generation and detection internal diagnostic capabilities ? loopback controls for communications link fault isolation ? break, parity, overrun, and framing error simulation modem control functions (cts, rts) the uart0 registers are listed in table 6-40 . table 6-40. uart0 register descriptions hex address range acronym register name 0x01c2 0000 rbr uart0 receiver buffer register (read only) 0x01c2 0000 thr uart0 transmitter holding register (write only) 0x01c2 0004 ier uart0 interrupt enable register 0x01c2 0008 iir uart0 interrupt identification register (read only) 0x01c2 0008 fcr uart0 fifo control register (write only) 0x01c2 000c lcr uart0 line control register 0x01c2 0010 mcr uart0 modem control register 0x01c2 0014 lsr uart0 line status register 0x01c2 0018 - reserved 0x01c2 001c - reserved 0x01c2 0020 dll uart0 divisor latch (lsb) 0x01c2 0024 dlh uart0 divisor latch (msb) 0x01c2 0028 pid1 peripheral identification register 1 0x01c2 002c pid2 peripheral identification register 2 0x01c2 0030 pwremu_mgmt uart0 power and emulation management register 0x01c2 0034 - 0x01c2 03ff - reserved peripheral information and electrical specifications 208 submit documentation feedback
6.11.2 uart electrical data/timing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-41. timing requirements for uartx receive (1) (see figure 6-24 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 4 t w(urxdb) pulse duration, receive data bit (urxdx) [15/30/100 pf] 0.96u 1.05u ns 5 t w(urxsb) pulse duration, receive start bit [15/30/100 pf] 0.96u 1.05u ns (1) u = uart baud time = 1/programmed baud rate. table 6-42. switching characteristics over recommended operating conditions for uartx transmit (1) (see figure 6-24 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 1 f (baud) maximum programmable baud rate 128 khz 2 t w(utxdb) pulse duration, transmit data bit (utxdx) [15/30/100 pf] u - 2 u + 2 ns 3 t w(utxsb) pulse duration, transmit start bit [15/30/100 pf] u - 2 u + 2 ns (1) u = uart baud time = 1/programmed baud rate. figure 6-24. uart transmit/receive timing submit documentation feedback peripheral information and electrical specifications 209 3 2 start bit data bits utxdx 5 data bits bit start 4 urxdx
6.12 inter-integrated circuit (i2c) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the inter-integrated circuit (i2c) module provides an interface between dm6433 and other devices compliant with philips semiconductors inter-ic bus (i 2 c-bus?) specification version 2.1. external components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the dsp through the i2c module. the i2c port does not support cbus compatible devices. the i2c port supports: compatible with philips i2c specification revision 2.1 (january 2000) fast mode up to 400 kbps (no fail-safe i/o buffers) noise filter to remove noise 50 ns or less seven- and ten-bit device addressing modes master (transmit/receive) and slave (transmit/receive) functionality events: dma, interrupt, or polling slew-rate limited open-drain output buffers figure 6-25. i2c module block diagram for more detailed information on the i2c peripheral, see section 2.9 , documentation support section of this document for the tms320dm643x dmp peripherals overview reference guide (literature number spru983). peripheral information and electrical specifications 210 submit documentation feedback clock prescale icpsc peripheral clock(dsp/18) icclkh generator bit clock icclkl noise filter scl icxsr icdxr transmit transmit shift transmitbuffer icdrr shift icrsr receivebuffer receive receive filter sda i2c data noise icoar icsar slaveaddress control address own icmdr iccnt modedata count vector interrupt interruptstatus icivr icstr mask/status interrupt icimr interrupt/dma i2c module i2c clock shading denotes control/status registers. icemdr extendedmode
6.12.1 i2c peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-43. i2c registers hex address range acronym register name 0x1c2 1000 icoar i2c own address register 0x1c2 1004 icimr i2c interrupt mask register 0x1c2 1008 icstr i2c interrupt status register 0x1c2 100c icclkl i2c clock divider low register 0x1c2 1010 icclkh i2c clock divider high register 0x1c2 1014 iccnt i2c data count register 0x1c2 1018 icdrr i2c data receive register 0x1c2 101c icsar i2c slave address register 0x1c2 1020 icdxr i2c data transmit register 0x1c2 1024 icmdr i2c mode register 0x1c2 1028 icivr i2c interrupt vector register 0x1c2 102c icemdr i2c extended mode register 0x1c2 1030 icpsc i2c prescaler register 0x1c2 1034 icpid1 i2c peripheral identification register 1 0x1c2 1038 icpid2 i2c peripheral identification register 2 submit documentation feedback peripheral information and electrical specifications 211
6.12.2 i2c electrical data/timing 6.12.2.1 inter-integrated circuits (i2c) timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-44. timing requirements for i2c timings (1) (see figure 6-26 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. standard unit fast mode mode min max min max 1 t c(scl) cycle time, scl 10 2.5 s setup time, scl high before sda low (for a repeated start 2 t su(sclh-sdal) 4.7 0.6 s condition) hold time, scl low after sda low (for a start and a repeated 3 t h(scll-sdal) 4 0.6 s start condition) 4 t w(scll) pulse duration, scl low 4.7 1.3 s 5 t w(sclh) pulse duration, scl high 4 0.6 s 6 t su(sdav-sclh) setup time, sda valid before scl high 250 100 (2) ns 7 t h(sda-scll) hold time, sda valid after scl low 0 (3) 0 (3) 0.9 (4) s pulse duration, sda high between stop and start 8 t w(sdah) 4.7 1.3 s conditions 9 t r(sda) rise time, sda 1000 20 + 0.1c b (5) 300 ns 10 t r(scl) rise time, scl 1000 20 + 0.1c b (5) 300 ns 11 t f(sda) fall time, sda 300 20 + 0.1c b (5) 300 ns 12 t f(scl) fall time, scl 300 20 + 0.1c b (5) 300 ns 13 t su(sclh-sdah) setup time, scl high before sda high (for stop condition) 4 0.6 s 14 t w(sp) pulse duration, spike (must be suppressed) 0 50 ns 15 c b (5) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) a fast-mode i 2 c-bus? device can be used in a standard-mode i 2 c-bus system, but the requirement t su(sda-sclh) 3 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su(sda-sclh) = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. (3) a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. (4) the maximum t h(sda-scll) has only to be met if the device does not stretch the low period [t w(scll) ] of the scl signal. (5) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 6-26. i2c receive timings peripheral information and electrical specifications 212 submit documentation feedback 10 8 4 3 7 12 5 6 14 2 3 13 stop start repeated start stop sda scl 1 11 9
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-45. switching characteristics for i2c timings (1) (see figure 6-27 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter standard unit fast mode mode min max min max 16 t c(scl) cycle time, scl 10 2.5 s delay time, scl high to sda low (for a repeated start 17 t d(sclh-sdal) 4.7 0.6 s condition) delay time, sda low to scl low (for a start and a repeated 18 t d(sdal-scll) 4 0.6 s start condition) 19 t w(scll) pulse duration, scl low 4.7 1.3 s 20 t w(sclh) pulse duration, scl high 4 0.6 s 21 t d(sdav-sclh) delay time, sda valid to scl high 250 100 ns 22 t v(scll-sdav) valid time, sda valid after scl low 0 0 0.9 s pulse duration, sda high between stop and start 23 t w(sdah) 4.7 1.3 s conditions 24 t r(sda) rise time, sda 1000 20 + 0.1c b (1) 300 ns 25 t r(scl) rise time, scl 1000 20 + 0.1c b (1) 300 ns 26 t f(sda) fall time, sda 300 20 + 0.1c b (1) 300 ns 27 t f(scl) fall time, scl 300 20 + 0.1c b (1) 300 ns 28 t d(sclh-sdah) delay time, scl high to sda high (for stop condition) 4 0.6 s 29 c p capacitance for each i2c pin 10 10 pf (1) c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, faster fall-times are allowed. figure 6-27. i2c transmit timings submit documentation feedback peripheral information and electrical specifications 213 25 23 19 18 22 27 20 21 17 18 28 stop start repeated start stop sda scl 16 26 24
6.13 host-port interface (hpi) peripheral 6.13.1 hpi device-specific information 6.13.2 hpi peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the dm6433 device includes a user-configurable 16-bit host-port interface (hpi16). software handshaking via the hrdy bit of the host port control register (hpic) is not supported on the dm6433. the dm6433 hpi does not support the has feature. for proper device operation, the has pin must be pulled up via an external resistor. table 6-46. hpi control registers hex address range acronym register name comments 01c6 7800 pid peripheral identification register the cpu has read/write 01c6 7804 pwremu_mgmt hpi power and emulation management register access to the pwremu_mgmt register. 01c6 7808 - 01c6 7824 - reserved 01c6 7828 - reserved 01c6 782c - reserved the host and the cpu both 01c6 7830 hpic hpi control register have read/write access to the hpic register. hpia hpi address register the host has read/write 01c6 7834 (hpiaw) (1) (write) access to the hpia registers. the cpu has only read hpia hpi address register 01c6 7838 access to the hpia registers. (hpiar) (1) (read) 01c6 780c - 01c6 7fff - reserved (1) there are two 32-bit hpia registers: hpiar for read operations and hpiaw for write operations. the hpi can be configured such that hpiar and hpiaw act as a single 32-bit hpia (single-hpia mode) or as two separate 32-bit hpias (dual-hpia mode) from the perspective of the host. the cpu can access hpiaw and hpiar independently. for more details about the hpia registers and their modes, see the tms320dm643x dmp host port interface (hpi) user's guide (literature number spru998 ). peripheral information and electrical specifications 214 submit documentation feedback
6.13.3 hpi electrical data/timing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-47. timing requirements for host-port interface cycles (1) (2) (see figure 6-28 and figure 6-29 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t su(selv-hstbl) setup time, select signals (3) valid before hstrobe low 5 ns 2 t h(hstbl-selv) hold time, select signals (3) valid after hstrobe low 2 ns 3 t w(hstbl) pulse duration, hstrobe active low 15 ns 4 t w(hstbh) pulse duration, hstrobe inactive high between consecutive accesses 2m ns 11 t su(hdv-hstbh) setup time, host data valid before hstrobe high 5 ns 12 t h(hstbh-hdv) hold time, host data valid after hstrobe high 0 ns hold time, hstrobe high after hrdy low. hstrobe should not be 13 t h(hrdyl-hstbl) inactivated until hrdy is active (low); otherwise, hpi writes will not 0 ns complete properly. (1) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (2) m = sysclk3 period = (cpu clock frequency)/6 in ns. for example, when running parts at 600 mhz, use m = 10 ns. (3) select signals include: hcntl[1:0], hr/ w and hhwil. submit documentation feedback peripheral information and electrical specifications 215
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-48. switching characteristics for host-port interface cycles (1) (2) (3) (see figure 6-28 and figure 6-29 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max for hpi write, hrdy can go high ( not ready) for these hpi write conditions; otherwise, hrdy stays low ( ready): case 1: back-to-back hpia writes (can be either first or second half-word) case 2: hpia write following a prefetch command (can be either first or second half-word) case 3: hpid write when fifo is full or flushing (can be either first or second half-word) case 4: hpia write and write fifo not empty for hpi read, hrdy can go high ( not ready) for these hpi read conditions: case 1: hpid read (with delay time, hstrobe low to 5 t d(hstbl-hrdyv) 12 ns auto-increment) and data not in read hrdy valid fifo (can only happen to first half-word of hpid access) case 2: first half-word access of hpid read without auto-increment for hpi read, hrdy stays low ( ready) for these hpi read conditions: case 1: hpid read with auto-increment and data is already in read fifo (applies to either half-word of hpid access) case 2: hpid read without auto-increment and data is already in read fifo (always applies to second half-word of hpid access) case 3: hpic or hpia read (applies to either half-word access) 6 t en(hstbl-hd) enable time, hd driven from hstrobe low 2 ns 7 t d(hrdyl-hdv) delay time, hrdy low to hd valid 0 ns 8 t oh(hstbh-hdv) output hold time, hd valid after hstrobe high 1.5 ns 14 t dis(hstbh-hdv) disable time, hd high-impedance from hstrobe high 12 ns for hpi read. applies to conditions where data is already residing in hpid/fifo: case 1: hpic or hpia read delay time, hstrobe low to 15 t d(hstbl-hdv) case 2: first half-word of hpid read 15 ns hd valid with auto-increment and data is already in read fifo case 3: second half-word of hpid read with or without auto-increment for hpi write, hrdy can go high ( not ready) for these hpi write conditions; otherwise, hrdy stays low ( ready): case 1: hpid write when write fifo is delay time, hstrobe high to full (can happen to either half-word) 18 t d(hstbh-hrdyv) 12 ns hrdy valid case 2: hpia write (can happen to either half-word) case 3: hpid write without auto-increment (only happens to second half-word) (1) m = sysclk3 period = (cpu clock frequency)/6 in ns. for example, when running parts at 600 mhz, use m = 10 ns. (2) hstrobe refers to the following logical operation on hcs, hds1, and hds2: [not( hds1 xor hds2)] or hcs. (3) by design, whenever hcs is driven inactive (high), hpi will drive hrdy active (low). peripheral information and electrical specifications 216 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-28. hpi16 read timing ( has not used, tied high) submit documentation feedback peripheral information and electrical specifications 217 hcs has (d) hcntl[1:0] hr/w hhwil hstrobe (a)(c) hd[15:0] (output) hrdy (b) 1 2 1 2 1 2 5 6 3 4 3 1 2 1 2 1 2 8 14 15 14 8 7 1st half-w ord 2nd half-w ord 6 13 15 a. hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur . for more detailed information on the hpi peripheral, see the tms320dm643x host port interface (hpi) user ' s guide (literature number spru998). c. hcs reflects typical hcs behavior when hstrobe assertion is caused by hds1 or hds2 . hcs timing requirements are reflected by parameters for hstrobe . d for proper hpi operation, has must be pulled up via an external resistor .
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 6-29. hpi16 write timing ( has not used, tied high) 218 peripheral information and electrical specifications submit documentation feedback has (d) hcntl[1:0] hr/w hhwil hstrobe (a)(c) hcs hd[15:0] (input) hrdy (b) 2 1 2 1 1 22 1 2 1 1 2 3 4 3 11 12 18 13 5 18 5 11 12 13 2nd half-w ord 1st half-w ord a. hstrobe refers to the following logical operation on hcs , hds1 , and hds2 : [not(hds1 xor hds2 )] or hcs . b. depending on the type of write or read operation (hpid without auto-incrementing; hpia, hpic, or hpid with auto-incrementing) and the state of the fifo, transitions on hrdy may or may not occur . for more detailed information on the hpi peripheral, see the tms320dm643x host port interface (hpi) user ' s guide (literature number spru998). c. hcs reflects typical hcs behavior when hstrobe assertion is caused by hds1 or hds2 . hcs timing requirements are reflected by parameters for hstrobe . d for proper hpi operation, has must be pulled up via an external resistor .
6.14 multichannel buffered serial port (mcbsp) 6.14.1 mcbsp peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the mcbsp provides these functions: full-duplex communication double-buffered data registers, which allow a continuous data stream independent framing and clocking for receive and transmit direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected analog-to-digital (a/d) and digital-to-analog (d/a) devices external shift clock or an internal, programmable frequency shift clock for data transfer if internal clock source is used, the clkgdv field of the sample rate generator register (srgr) must always be set to a value of 1 or greater. for more detailed information on the mcbsp peripheral, see the tms320dm643x dmp multichannel buffered serial port (mcbsp) user's guide (literature number spru943 ). table 6-49. mcbsp 0 registers hex address range acronym register name comments the cpu and edma3 controller can only read 01d0 0000 drr0 mcbsp0 data receive register this register; they cannot write to it. 01d0 0004 dxr0 mcbsp0 data transmit register 01d0 0008 spcr0 mcbsp0 serial port control register 01d0 000c rcr0 mcbsp0 receive control register 01d0 0010 xcr0 mcbsp0 transmit control register 01d0 0014 srgr0 mcbsp0 sample rate generator register 01d0 0018 mcr0 mcbsp0 multichannel control register mcbsp0 enhanced receive channel enable register 01d0 001c rcere00 0 partition a/b mcbsp0 enhanced transmit channel enable register 01d0 0020 xcere00 0 partition a/b 01d0 0024 pcr0 mcbsp0 pin control register mcbsp0 enhanced receive channel enable register 01d0 0028 rcere10 1 partition c/d mcbsp0 enhanced transmit channel enable register 01d0 002c xcere10 1 partition c/d mcbsp0 enhanced receive channel enable register 01d0 0030 rcere20 2 partition e/f mcbsp0 enhanced transmit channel enable register 01d0 0034 xcere20 2 partition e/f mcbsp0 enhanced receive channel enable register 01d0 0038 rcere30 3 partition g/h mcbsp0 enhanced transmit channel enable register 01d0003c xcere30 3 partition g/h 01d0 0040 - 01d0 07ff - reserved submit documentation feedback peripheral information and electrical specifications 219
6.14.2 mcbsp electrical data/timing 6.14.2.1 multichannel buffered serial port (mcbsp) timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-50. timing requirements for mcbsp (1) (see figure 6-30 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 2 t c(ckrx) cycle time, clkr/x clkr/x ext 2p (2) (3) ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p - 1 (4) ns clkr int 14 5 t su(frh-ckrl) setup time, external fsr high before clkr low ns clkr ext 4 clkr int 6 6 t h(ckrl-frh) hold time, external fsr high after clkr low ns clkr ext 4 clkr int 14 7 t su(drv-ckrl) setup time, dr valid before clkr low ns clkr ext 4 clkr int 3 8 t h(ckrl-drv) hold time, dr valid after clkr low ns clkr ext 3.5 clkx int 14 10 t su(fxh-ckxl) setup time, external fsx high before clkx low ns clkx ext 4 clkx int 6 11 t h(ckxl-fxh) hold time, external fsx high after clkx low ns clkx ext 3 (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (3) use whichever value is greater. minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. the minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (4) this parameter applies to the maximum mcbsp frequency. operate serial clocks (clkr/x) in the reasonable range of 40/60 duty cycle. peripheral information and electrical specifications 220 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-51. switching characteristics over recommended operating conditions for mcbsp (1) (2) (see figure 6-30 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max delay time, clks high to clkr/x high for internal clkr/x 1 t d(cksh-ckrxh) 3 10 ns generated from clks input 2 t c(ckrx) cycle time, clkr/x clkr/x int 2p (3) (4) (5) ns 3 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x int c - 2 (6) c + 2 (6) ns 4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int -4 5.5 ns clkx int -4 5.5 9 t d(ckxh-fxv) delay time, clkx high to internal fsx valid ns clkx ext 2.5 14.5 clkx int -5.5 7.5 disable time, dx high impedance following 12 t dis(ckxh-dxhz) ns last data bit from clkx high clkx ext -2.1 16 clkx int -4 + d1 (7) 5.5 + d2 (7) 13 t d(ckxh-dxv) delay time, clkx high to dx valid ns clkx ext 2.5 + d1 (7) 14.5 + d2 (7) delay time, fsx high to dx valid fsx int -4 (8) 5 (8) 14 t d(fxh-dxv) ns only applies when in data fsx ext 1 (8) 14.5 (8) delay 0 (xdatdly = 00b) mode (1) clkrp = clkxp = fsrp = fsxp = 0. if polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) minimum delay times also represent minimum output hold times. (3) minimum clkr/x cycle times must be met, even when clkr/x is generated by an internal clock source. minimum clkr/x cycle times are based on internal logic speed; the maximum usable speed may be lower due to edma limitations and ac timing requirements. (4) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (5) use whichever value is greater. (6) c = h or l s = sample rate generator input clock = p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = p_clks if clksm = 0 (p_clks = clks period) h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd clkgdv should be set appropriately to ensure the mcbsp bit rate does not exceed the maximum limit (see (4) above). (7) extra delay from clkx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p (8) extra delay from fsx high to dx valid applies only to the first data bit of a device, if and only if dxena = 1 in spcr. if dxena = 0, then d1 = d2 = 0 if dxena = 1, then d1 = 6p, d2 = 12p submit documentation feedback peripheral information and electrical specifications 221
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com a. parameter no. 13 applies to the first data bit only when xdatdly 1 0. figure 6-30. mcbsp timing (b) table 6-52. timing requirements for fsr when gsync = 1 (see figure 6-31 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t su(frh-cksh) setup time, fsr high before clks high 4 ns 2 t h(cksh-frh) hold time, fsr high after clks high 4 ns figure 6-31. fsr timing when gsync = 1 peripheral information and electrical specifications 222 submit documentation feedback 2 1 clks fsr external clkr/x (no need to resync) clkr/x (needs resync) bit(n-1) (n-2) (n-3) bit 0 bit(n-1) (n-2) (n-3) 14 12 11 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 clks clkr fsr (int) fsr (ext) dr clkx fsx (int) fsx (ext) fsx (xda tdly=00b) dx 13 (a) 13 (a)
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-53. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 6-32 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit master slave min max min max 4 t su(drv-ckxl) setup time, dr valid before clkx low 14 2 - 3p ns 5 t h(ckxl-drv) hold time, dr valid after clkx low 4 5 + 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. table 6-54. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 0 (1) (2) (see figure 6-32 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit master (3) slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) t - 4 t + 5.5 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) l - 4 l + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) l - 6 l + 7.5 ns last data bit from clkx low disable time, dx high impedance following 7 t dis(fxh-dxhz) p + 3 3p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 1.8 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-32. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 submit documentation feedback peripheral information and electrical specifications 223 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 76 2 1 clkx fsx dx dr
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-55. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 6-33 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. peripheral information and electrical specifications 224 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-56. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 0 (1) (2) (see figure 6-33 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit master (3) slave min max min max 1 t h(ckxl-fxl) hold time, fsx low after clkx low (4) l - 4 l + 5.5 ns 2 t d(fxl-ckxh) delay time, fsx low to clkx high (5) t - 4 t + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxl-dxhz) -6 7.5 3p + 2 5p + 17 ns last data bit from clkx low 7 t d(fxl-dxv) delay time, fsx low to dx valid h - 4 h + 5.5 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-33. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 table 6-57. timing requirements for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 6-34 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5 + 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. submit documentation feedback peripheral information and electrical specifications 225 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 clkx fsx dx dr 5
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-58. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 10b, clkxp = 1 (1) (2) (see figure 6-34 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit master (3) slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) t - 4 t + 5.5 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) h - 4 h + 4 ns 3 t d(ckxl-dxv) delay time, clkx low to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) h - 6 h + 7.5 ns last data bit from clkx high disable time, dx high impedance following 7 t dis(fxh-dxhz) p + 3 3p + 17 ns last data bit from fsx high 8 t d(fxl-dxv) delay time, fsx low to dx valid 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-34. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 table 6-59. timing requirements for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 6-35 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit master slave min max min max 4 t su(drv-ckxh) setup time, dr valid before clkx high 14 2 - 3p ns 5 t h(ckxh-drv) hold time, dr valid after clkx high 4 5+ 6p ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. peripheral information and electrical specifications 226 submit documentation feedback bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 clkx fsx dx dr
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-60. switching characteristics over recommended operating conditions for mcbsp as spi master or slave: clkstp = 11b, clkxp = 1 (1) (2) (see figure 6-35 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit master (3) slave min max min max 1 t h(ckxh-fxl) hold time, fsx low after clkx high (4) h - 4 h + 5.5 ns 2 t d(fxl-ckxl) delay time, fsx low to clkx low (5) t - 4 t + 4 ns 3 t d(ckxh-dxv) delay time, clkx high to dx valid -4 5.5 3p + 2.8 5p + 17 ns disable time, dx high impedance following 6 t dis(ckxh-dxhz) -6 7.5 3p + 2 5p + 17 ns last data bit from clkx high 7 t d(fxl-dxv) delay time, fsx low to dx valid l - 4 l+ 5.5 2p + 2 4p + 17 ns (1) p = sysclk3 period in ns. for example, when running parts at 600 mhz, use p = 10 ns. (2) for all spi slave modes, the rate of the internal clock clkg must be at least 8 times faster than that of the spi data rate. user should program sample rate generator to achieve maximum clkg by setting clksm = clkgdv = 1. (3) s = sample rate generator input clock = 2p if clksm = 1 (p = sysclk3 period) s = sample rate generator input clock = 2p_clks if clksm = 0 (p_clks = clks period) t = clkx period = (1 + clkgdv) * s h = clkx high pulse width = (clkgdv/2 + 1) * s if clkgdv is even h = (clkgdv + 1)/2 * s if clkgdv is odd l = clkx low pulse width = (clkgdv/2) * s if clkgdv is even l = (clkgdv + 1)/2 * s if clkgdv is odd (4) fsrp = fsxp = 1. as a spi master, fsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on fsx and fsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp (5) fsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (clkx). figure 6-35. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 submit documentation feedback peripheral information and electrical specifications 227 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 clkx fsx dx dr
6.15 multichannel audio serial port (mcasp0) peripheral 6.15.1 mcasp0 device-specific information tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the mcasp functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications. the mcasp is useful for time-division multiplexed (tdm) stream, inter-integrated sound (i2s) protocols, and intercomponent digital audio interface transmission (dit). the dm6433 device includes one multichannel audio serial port (mcasp) interface peripheral (mcasp0). the mcasp0 is a serial port optimized for the needs of multichannel audio applications. the mcasp0 consists of a transmit and receive section. these sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. the mcasp module also includes a pool of 16 shift registers that may be configured to operate as either transmit data or receive data. the transmit section of the mcasp can transmit data in either a time-division-multiplexed (tdm) synchronous serial format or in a digital audio interface (dit) format where the bit stream is encoded for s/pdif, aes-3, iec-60958, cp-430 transmission. the receive section of the mcasp supports the tdm synchronous serial format. the mcasp can support one transmit data format (either a tdm format or dit format) and one receive format at a time. all transmit shift registers use the same format and all receive shift registers use the same format. however, the transmit and receive formats need not be the same. both the transmit and receive sections of the mcasp also support burst mode which is useful for non-audio data (for example, passing control information between two dsps). the mcasp peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. for more detailed information on and the functionality of the mcasp0 peripheral, see the tms320dm643x dmp multichannel audio serial port (mcasp) user's guide (literature number spru980). peripheral information and electrical specifications 228 submit documentation feedback
6.15.1.1 mcasp block diagram tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 figure 6-36 illustrates the major blocks along with external signals of the tms320dm6433 mcasp0 peripheral; and shows the 4 serial data [axr] pins. figure 6-36. mcasp0 configuration submit documentation feedback peripheral information and electrical specifications 229 receive clock generator ahclkr0aclkr0 t generator clock transmit aclkx0 ahclkx0 dit ram transmit generator frame sync afsx0 detect error receive frame sync generator formatter transmit data amute0amutein0 afsr0 serializer 0 serializer 1 serializer 3 serializer 2 clock check ransmit (high- frequency) receive clock check (high- frequency) receive formatter data mcasp0 dms t ransmit dma receive individually programmable tx/rx/gpio control gpio axr0[0]axr0[1] axr0[3] axr0[2]
6.15.1.2 mcasp0 peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-61. mcasp0 control registers hex address range acronym register name 01d0 1000 pid peripheral identification register [register value: 0x0010 0101] 01d0 1004 ? reserved 01d0 1008 ? reserved 01d0 100c ? reserved 01d0 1010 pfunc pin function register 01d0 1014 pdir pin direction register 01d0 1018 ? reserved 01d0 101c ? reserved 01d0 1020 ? reserved 01d0 1024 ? 01d0 1040 ? reserved 01d0 1044 gblctl global control register 01d0 1048 amute mute control register 01d0 104c dlbctl digital loop-back control register 01d0 1050 ditctl dit mode control register 01d0 1054 ? 01d0 105c ? reserved alias of gblctl containing only receiver reset bits, allows transmit to be reset 01d0 1060 rgblctl independently from receive. 01d0 1064 rmask receiver format unit bit mask register 01d0 1068 rfmt receive bit stream format register 01d0 106c afsrctl receive frame sync control register 01d0 1070 aclkrctl receive clock control register 01d0 1074 ahclkrctl high-frequency receive clock control register 01d0 1078 rtdm receive tdm slot 0?31 register 01d0 107c rintctl receiver interrupt control register 01d0 1080 rstat status register ? receiver 01d0 1084 rslot current receive tdm slot register 01d0 1088 rclkchk receiver clock check control register 01d0 108c ? 01d0 109c ? reserved alias of gblctl containing only transmitter reset bits, allows transmit to be reset 01d0 10a0 xgblctl independently from receive. 01d0 10a4 xmask transmit format unit bit mask register 01d0 10a8 xfmt transmit bit stream format register 01d0 10ac afsxctl transmit frame sync control register 01d0 10b0 aclkxctl transmit clock control register 01d0 10b4 ahclkxctl high-frequency transmit clock control register 01d0 10b8 xtdm transmit tdm slot 0?31 register 01d0 10bc xintctl transmit interrupt control register 01d0 10c0 xstat status register ? transmitter 01d0 10c4 xslot current transmit tdm slot 01d0 10c8 xclkchk transmit clock check control register 230 peripheral information and electrical specifications submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-61. mcasp0 control registers (continued) hex address range acronym register name 01d0 10cc ? 01d0 10fc ? reserved 01d0 1100 ditcsra0 left (even tdm slot) channel status register file 01d0 1104 ditcsra1 left (even tdm slot) channel status register file 01d0 1108 ditcsra2 left (even tdm slot) channel status register file 01d0 110c ditcsra3 left (even tdm slot) channel status register file 01d0 1110 ditcsra4 left (even tdm slot) channel status register file 01d0 1114 ditcsra5 left (even tdm slot) channel status register file 01d0 1118 ditcsrb0 right (odd tdm slot) channel status register file 01d0 111c ditcsrb1 right (odd tdm slot) channel status register file 01d0 1120 ditcsrb2 right (odd tdm slot) channel status register file 01d0 1124 ditcsrb3 right (odd tdm slot) channel status register file 01d0 1128 ditcsrb4 right (odd tdm slot) channel status register file 01d0 112c ditcsrb5 right (odd tdm slot) channel status register file 01d0 1130 ditudra0 left (even tdm slot) user data register file 01d0 1134 ditudra1 left (even tdm slot) user data register file 01d0 1138 ditudra2 left (even tdm slot) user data register file 01d0 113c ditudra3 left (even tdm slot) user data register file 01d0 1140 ditudra4 left (even tdm slot) user data register file 01d0 1144 ditudra5 left (even tdm slot) user data register file 01d0 1148 ditudrb0 right (odd tdm slot) user data register file 01d0 114c ditudrb1 right (odd tdm slot) user data register file 01d0 1150 ditudrb2 right (odd tdm slot) user data register file 01d0 1154 ditudrb3 right (odd tdm slot) user data register file 01d0 1158 ditudrb4 right (odd tdm slot) user data register file 01d0 115c ditudrb5 right (odd tdm slot) user data register file 01d0 1160 ? 01d0 117c ? reserved 01d0 1180 srctl0 serializer 0 control register 01d0 1184 srctl1 serializer 1 control register 01d0 1188 srctl2 serializer 2 control register 01d0 118c srctl3 serializer 3 control register 01d0 1190 ? 01d0 11fc ? reserved 01d0 1200 xbuf0 transmit buffer for serializer 0 01d0 1204 xbuf1 transmit buffer for serializer 1 01d0 1208 xbuf2 transmit buffer for serializer 2 01d0 120c xbuf3 transmit buffer for serializer 3 01d0 1210 ? 01d0 127c ? reserved 01d0 1280 rbuf0 receive buffer for serializer 0 01d0 1284 rbuf1 receive buffer for serializer 1 01d0 1288 rbuf2 receive buffer for serializer 2 01d0 128c rbuf3 receive buffer for serializer 3 01d0 1290 ? 01d0 13ff ? reserved table 6-62. mcasp0 data registers hex address range acronym register name comments (used when rsel or xsel mcasp0 receive buffers or mcasp0 transmit buffers via bits = 0 [these bits are located 01d0 1400 ? 01d0 17ff rbuf/xbuf the peripheral data bus. in the rfmt or xfmt registers, respectively].) submit documentation feedback peripheral information and electrical specifications 231
6.15.1.3 mcasp0 electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com 6.15.1.3.1 multichannel audio serial port (mcasp) timing table 6-63. timing requirements for mcasp (see figure 6-37 and figure 6-38 ) (1) -7/-6/-5/-4 -l/-q6/-q5/- no. unit q4 min max 1 t c(ahckrx) cycle time, ahclkr/x 25 ns 2 t w(ahckrx) pulse duration, ahclkr/x high or low 10 ns 3 t c(ckrx) cycle time, aclkr/x aclkr/x ext 25 ns 4 t w(ckrx) pulse duration, aclkr/x high or low aclkr/x ext 10 ns aclkr/x int 11 ns 5 t su(frx-ckrx) setup time, afsr/x input valid before aclkr/x latches data aclkr/x ext 3 ns aclkr/x int 0 ns 6 t h(ckrx-frx) hold time, afsr/x input valid after aclkr/x latches data aclkr/x ext input 4 ns aclkr/x ext output 6 ns aclkr/x int 11 ns 7 t su(axr-ckrx) setup time, axr input valid before aclkr/x latches data aclkr/x ext 3 ns aclkr/x int 3 ns 8 t h(ckrx-axr) hold time, axr input valid after aclkr/x latches data aclkr/x ext input 4 ns aclkr/x ext output 6 ns (1) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 peripheral information and electrical specifications 232 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-64. switching characteristics over recommended operating conditions for mcasp (1) (2) (see figure 6-37 and figure 6-38 ) (3) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 9 t c(ahckrx) cycle time, ahclkr/x 25 ns 10 t w(ahckrx) pulse duration, ahclkr/x high or low ah - 2.5 ns aclkr/x 11 t c(ckrx) cycle time, aclkr/x 25 ns int aclkr/x 12 t w(ckrx) pulse duration, aclkr/x high or low a - 2.5 ns int aclkr/x -2.25 5.5 ns int aclkr/x 13 t d(ckrx-frx) delay time, aclkr/x transmit edge to afsx/r output valid 0 12.5 ns ext input aclkr/x 0 14 ns ext output aclkx int -2.25 5.5 ns aclkx 0 12.5 ns 14 t d(ckx-axrv) delay time, aclkx transmit edge to axr output valid ext input aclkx 0 14 ns ext output aclkr/x -4.5 8 ns int disable time, axr high impedance following last data bit from 15 t dis(ckrx-axrhz) aclkr/x transmit edge aclkr/x -4.5 12.5 ns ext (1) a = (aclkr/x period)/2 in ns. for example, when aclkr/x period is 25 ns, use a = 12.5 ns. (2) ah = (ahclkr/x period)/2 in ns. for example, when ahclkr/x period is 25 ns, use ah = 12.5 ns. (3) aclkx internal: aclkxctl.clkxm=1, pdir.aclkx = 1 aclkx external input: aclkxctl.clkxm=0, pdir.aclkx=0 aclkx external output: aclkxctl.clkxm=0, pdir.aclkx=1 aclkr internal: aclkrctl.clkrm=1, pdir.aclkr = 1 aclkr external input: aclkrctl.clkrm=0, pdir.aclkr=0 aclkr external output: aclkrctl.clkrm=0, pdir.aclkr=1 submit documentation feedback peripheral information and electrical specifications 233
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com a. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). b. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). figure 6-37. mcasp input timings 234 peripheral information and electrical specifications submit documentation feedback 8 7 4 4 3 2 2 1 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay)afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay)afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data in/receive) 6 5 aclkr/x (clkrp = clkxp = 0) (a) aclkr/x (clkrp = clkxp = 1) (b)
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 a. for clkrp = clkxp = 1, the mcasp transmitter is configured for falling edge (to shift data out) and the mcasp receiver is configured for rising edge (to shift data in). b. for clkrp = clkxp = 0, the mcasp transmitter is configured for rising edge (to shift data out) and the mcasp receiver is configured for falling edge (to shift data in). figure 6-38. mcasp output timings submit documentation feedback peripheral information and electrical specifications 235 15 14 13 13 13 13 13 13 13 12 12 11 10 10 9 a0 a1 b0 b1 a30 a31 b30 b31 c0 c1 c2 c3 c31 ahclkr/x (falling edge polarity) ahclkr/x (rising edge polarity) afsr/x (bit width, 0 bit delay) afsr/x (bit width, 1 bit delay) afsr/x (bit width, 2 bit delay) afsr/x (slot width, 0 bit delay) afsr/x (slot width, 1 bit delay) afsr/x (slot width, 2 bit delay) axr[n] (data out/t ransmit) aclkr/x (clkrp = clkxp = 0) (b) aclkr/x (clkrp = clkxp = 1) (a)
6.16 ethernet media access controller (emac) 6.16.1 emac peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com the ethernet media access controller (emac) provides an efficient interface between dm6433 and the network. the dm6433 emac supports both 10base-t (10 mbits/second [mbps]) and 100base-tx (100 mbps) in either half- or full-duplex mode. the emac module also supports hardware flow control and quality of service (qos) support. the emac controls the flow of packet data from the dm6433 device to the phy. the mdio module controls phy configuration and status monitoring. the emac module conforms to the ieee 802.3-2002 standard, describing the ?carrier sense multiple access with collision detection (csma/cd) access method and physical layer? specifications. the ieee 802.3 standard has also been adopted by iso/iec and re-designated as iso/iec 8802-3:2000(e). deviation from this standard, the emac module does not use the transmit coding error signal mtxer. instead of driving the error pin when an underflow condition occurs on a transmitted frame, the emac will intentionally generate an incorrect checksum by inverting the frame crc, so that the transmitted frame will be detected as an error by the network. both the emac and the mdio modules interface to the dm6433 device through a custom interface that allows efficient data transmission and reception. this custom interface is referred to as the emac control module, and is considered integral to the emac/mdio peripheral. the control module is also used to multiplex and control interrupts. for the dm6433 ethernet media access controller (emac)/management data input/output (mdio) module user's guide (literature number spru941) which describes the dm6433 emac peripheral in detail, see section 2.9 , documentation support section . for a list of supported registers and register fields, see table 6-65 [ethernet mac (emac) control registers] and table 6-66 [emac statistics registers] in this data manual. table 6-65. ethernet mac (emac) control registers hex address range acronym register name 01c8 0000 txidver transmit identification and version register 01c8 0004 txcontrol transmit control register 01c8 0008 txteardown transmit teardown register 01c8 0010 rxidver receive identification and version register 01c8 0014 rxcontrol receive control register 01c8 0018 rxteardown receive teardown register 01c8 0080 txintstatraw transmit interrupt status (unmasked) register 01c8 0084 txintstatmasked transmit interrupt status (masked) register 01c8 0088 txintmaskset transmit interrupt mask set register 01c8 008c txintmaskclear transmit interrupt mask clear register 01c8 0090 macinvector mac input vector register 01c8 00a0 rxintstatraw receive interrupt status (unmasked) register 01c8 00a4 rxintstatmasked receive interrupt status (masked) register 01c8 00a8 rxintmaskset receive interrupt mask set register 01c8 00ac rxintmaskclear receive interrupt mask clear register 01c8 00b0 macintstatraw mac interrupt status (unmasked) register 01c8 00b4 macintstatmasked mac interrupt status (masked) register 01c8 00b8 macintmaskset mac interrupt mask set register 01c8 00bc macintmaskclear mac interrupt mask clear register 01c8 0100 rxmbpenable receive multicast/broadcast/promiscuous channel enable register 01c8 0104 rxunicastset receive unicast enable set register peripheral information and electrical specifications 236 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-65. ethernet mac (emac) control registers (continued) hex address range acronym register name 01c8 0108 rxunicastclear receive unicast clear register 01c8 010c rxmaxlen receive maximum length register 01c8 0110 rxbufferoffset receive buffer offset register 01c8 0114 rxfilterlowthresh receive filter low priority frame threshold register 01c8 0120 rx0flowthresh receive channel 0 flow control threshold register 01c8 0124 rx1flowthresh receive channel 1 flow control threshold register 01c8 0128 rx2flowthresh receive channel 2 flow control threshold register 01c8 012c rx3flowthresh receive channel 3 flow control threshold register 01c8 0130 rx4flowthresh receive channel 4 flow control threshold register 01c8 0134 rx5flowthresh receive channel 5 flow control threshold register 01c8 0138 rx6flowthresh receive channel 6 flow control threshold register 01c8 013c rx7flowthresh receive channel 7 flow control threshold register 01c8 0140 rx0freebuffer receive channel 0 free buffer count register 01c8 0144 rx1freebuffer receive channel 1 free buffer count register 01c8 0148 rx2freebuffer receive channel 2 free buffer count register 01c8 014c rx3freebuffer receive channel 3 free buffer count register 01c8 0150 rx4freebuffer receive channel 4 free buffer count register 01c8 0154 rx5freebuffer receive channel 5 free buffer count register 01c8 0158 rx6freebuffer receive channel 6 free buffer count register 01c8 015c rx7freebuffer receive channel 7 free buffer count register 01c8 0160 maccontrol mac control register 01c8 0164 macstatus mac status register 01c8 0168 emcontrol emulation control register 01c8 016c fifocontrol fifo control register (transmit and receive) 01c8 0170 macconfig mac configuration register 01c8 0174 softreset soft reset register 01c8 01d0 macsrcaddrlo mac source address low bytes register (lower 32-bits) 01c8 01d4 macsrcaddrhi mac source address high bytes register (upper 16-bits) 01c8 01d8 machash1 mac hash address register 1 01c8 01dc machash2 mac hash address register 2 01c8 01e0 bofftest back off test register 01c8 01e4 tpacetest transmit pacing algorithm test register 01c8 01e8 rxpause receive pause timer register 01c8 01ec txpause transmit pause timer register 01c8 0200 - 01c8 02fc (see table 6-66 ) emac statistics registers 01c8 0500 macaddrlo mac address low bytes register 01c8 0504 macaddrhi mac address high bytes register 01c8 0508 macindex mac index register 01c8 0600 tx0hdp transmit channel 0 dma head descriptor pointer register 01c8 0604 tx1hdp transmit channel 1 dma head descriptor pointer register 01c8 0608 tx2hdp transmit channel 2 dma head descriptor pointer register 01c8 060c tx3hdp transmit channel 3 dma head descriptor pointer register 01c8 0610 tx4hdp transmit channel 4 dma head descriptor pointer register 01c8 0614 tx5hdp transmit channel 5 dma head descriptor pointer register 01c8 0618 tx6hdp transmit channel 6 dma head descriptor pointer register 01c8 061c tx7hdp transmit channel 7 dma head descriptor pointer register 01c8 0620 rx0hdp receive channel 0 dma head descriptor pointer register submit documentation feedback peripheral information and electrical specifications 237
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-65. ethernet mac (emac) control registers (continued) hex address range acronym register name 01c8 0624 rx1hdp receive channel 1 dma head descriptor pointer register 01c8 0628 rx2hdp receive channel 2 dma head descriptor pointer register 01c8 062c rx3hdp receive channel 3 dma head descriptor pointer register 01c8 0630 rx4hdp receive channel 4 dma head descriptor pointer register 01c8 0634 rx5hdp receive channel 5 dma head descriptor pointer register 01c8 0638 rx6hdp receive channel 6 dma head descriptor pointer register 01c8 063c rx7hdp receive channel 7 dma head descriptor pointer register transmit channel 0 completion pointer (interrupt acknowledge) 01c8 0640 tx0cp register transmit channel 1 completion pointer (interrupt acknowledge) 01c8 0644 tx1cp register transmit channel 2 completion pointer (interrupt acknowledge) 01c8 0648 tx2cp register transmit channel 3 completion pointer (interrupt acknowledge) 01c8 064c tx3cp register transmit channel 4 completion pointer (interrupt acknowledge) 01c8 0650 tx4cp register transmit channel 5 completion pointer (interrupt acknowledge) 01c8 0654 tx5cp register transmit channel 6 completion pointer (interrupt acknowledge) 01c8 0658 tx6cp register transmit channel 7 completion pointer (interrupt acknowledge) 01c8 065c tx7cp register receive channel 0 completion pointer (interrupt acknowledge) 01c8 0660 rx0cp register receive channel 1 completion pointer (interrupt acknowledge) 01c8 0664 rx1cp register receive channel 2 completion pointer (interrupt acknowledge) 01c8 0668 rx2cp register receive channel 3 completion pointer (interrupt acknowledge) 01c8 066c rx3cp register receive channel 4 completion pointer (interrupt acknowledge) 01c8 0670 rx4cp register receive channel 5 completion pointer (interrupt acknowledge) 01c8 0674 rx5cp register receive channel 6 completion pointer (interrupt acknowledge) 01c8 0678 rx6cp register receive channel 7 completion pointer (interrupt acknowledge) 01c8 067c rx7cp register 238 peripheral information and electrical specifications submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-66. emac statistics registers hex address range acronym register name 01c8 0200 rxgoodframes good receive frames register broadcast receive frames register 01c8 0204 rxbcastframes (total number of good broadcast frames received) multicast receive frames register 01c8 0208 rxmcastframes (total number of good multicast frames received) 01c8 020c rxpauseframes pause receive frames register receive crc errors register (total number of frames received with 01c8 0210 rxcrcerrors crc errors) receive alignment/code errors register 01c8 0214 rxaligncodeerrors (total number of frames received with alignment/code errors) receive oversized frames register 01c8 0218 rxoversized (total number of oversized frames received) receive jabber frames register 01c8 021c rxjabber (total number of jabber frames received) receive undersized frames register 01c8 0220 rxundersized (total number of undersized frames received) 01c8 0224 rxfragments receive frame fragments register 01c8 0228 rxfiltered filtered receive frames register 01c8 022c rxqosfiltered received qos filtered frames register receive octet frames register 01c8 0230 rxoctets (total number of received bytes in good frames) good transmit frames register 01c8 0234 txgoodframes (total number of good frames transmitted) 01c8 0238 txbcastframes broadcast transmit frames register 01c8 023c txmcastframes multicast transmit frames register 01c8 0240 txpauseframes pause transmit frames register 01c8 0244 txdeferred deferred transmit frames register 01c8 0248 txcollision transmit collision frames register 01c8 024c txsinglecoll transmit single collision frames register 01c8 0250 txmulticoll transmit multiple collision frames register 01c8 0254 txexcessivecoll transmit excessive collision frames register 01c8 0258 txlatecoll transmit late collision frames register 01c8 025c txunderrun transmit underrun error register 01c8 0260 txcarriersense transmit carrier sense errors register 01c8 0264 txoctets transmit octet frames register 01c8 0268 frame64 transmit and receive 64 octet frames register 01c8 026c frame65t127 transmit and receive 65 to 127 octet frames register 01c8 0270 frame128t255 transmit and receive 128 to 255 octet frames register 01c8 0274 frame256t511 transmit and receive 256 to 511 octet frames register 01c8 0278 frame512t1023 transmit and receive 512 to 1023 octet frames register 01c8 027c frame1024tup transmit and receive 1024 to 1518 octet frames register 01c8 0280 netoctets network octet frames register 01c8 0284 rxsofoverruns receive fifo or dma start of frame overruns register 01c8 0288 rxmofoverruns receive fifo or dma middle of frame overruns register receive dma start of frame and middle of frame overruns 01c8 028c rxdmaoverruns register submit documentation feedback peripheral information and electrical specifications 239
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-67. emac control module registers hex address range acronym register name 0x01c8 1004 ewctl interrupt control register 0x01c8 1008 ewinttcnt interrupt timer count table 6-68. emac control module ram hex address range acronym register name 0x01c8 2000 - 0x01c8 3fff emac control module descriptor memory peripheral information and electrical specifications 240 submit documentation feedback
6.16.2 emac electrical data/timing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-69. timing requirements for mrclk (see figure 6-39 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit 10 mbps 100 mbps min max min max 1 t c(mrclk) cycle time, mrclk 400 40 ns 2 t w(mrclkh) pulse duration, mrclk high 140 14 ns 3 t w(mrclkl) pulse duration, mrclk low 140 14 ns figure 6-39. mrclk timing (emac - receive) table 6-70. timing requirements for mtclk (see figure 6-39 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit 10 mbps 100 mbps min max min max 1 t c(mtclk) cycle time, mtclk 400 40 ns 2 t w(mtclkh) pulse duration, mtclk high 140 14 ns 3 t w(mtclkl) pulse duration, mtclk low 140 14 ns figure 6-40. mtclk timing (emac - transmit) table 6-71. timing requirements for emac mii receive 10/100 mbit/s (1) (see figure 6-41 ) -7/-6/-5/-4 -l/-q6/-q5/- no. unit q4 min max 1 t su(mrxd-mrclkh) setup time, receive selected signals valid before mrclk high 8 ns 2 t h(mrclkh-mrxd) hold time, receive selected signals valid after mrclk high 8 ns (1) receive selected signals include: mrxd3-mrxd0, mrxdv, and mrxer. submit documentation feedback peripheral information and electrical specifications 241 mrclk 2 3 1 mtclk 2 3 1
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com figure 6-41. emac receive interface timing table 6-72. switching characteristics over recommended operating conditions for emac mii transmit 10/100 mbit/s (1) (see figure 6-42 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t d(mtclkh-mtxd) delay time, mtclk high to transmit selected signals valid 2 25 ns (1) transmit selected signals include: mtxd3-mtxd0, and mtxen. figure 6-42. emac transmit interface timing 242 peripheral information and electrical specifications submit documentation feedback mrclk (input) 1 2 mrxd3?mrxd0, mrxdv , mrxer (inputs) 1 mtclk (input) mtxd3?mtxd0, mtxen (outputs)
6.17 management data input/output (mdio) 6.17.1 peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the management data input/output (mdio) module continuously polls all 32 mdio addresses in order to enumerate all phy devices in the system. the management data input/output (mdio) module implements the 802.3 serial management interface to interrogate and control ethernet phy(s) using a shared two-wire bus. host software uses the mdio module to configure the auto-negotiation parameters of each phy attached to the emac, retrieve the negotiation results, and configure required parameters in the emac module for correct operation. the module is designed to allow almost transparent operation of the mdio interface, with very little maintenance from the core processor. only one phy may be connected at any given time. for more detailed information on the mdio peripheral, see the documentation support section for the ethernet media access controller (emac)/management data input/output (mdio) module reference guide. for a list of supported registers and register fields, see table 6-73 [mdio registers] in this data manual. table 6-73. mdio registers hex address range acronym register name 0x01c8 4000 ? reserved 0x01c8 4004 control mdio control register 0x01c8 4008 alive mdio phy alive status register 0x01c8 400c link mdio phy link status register 0x01c8 4010 linkintraw mdio link status change interrupt (unmasked) register 0x01c8 4014 linkintmasked mdio link status change interrupt (masked) register 0x01c8 4018 ? reserved 0x01c8 4020 userintraw mdio user command complete interrupt (unmasked) register 0x01c8 4024 userintmasked mdio user command complete interrupt (masked) register 0x01c8 4028 userintmaskset mdio user command complete interrupt mask set register 0x01c8 402c userintmaskclear mdio user command complete interrupt mask clear register 0x01c8 4030 - 0x01c8 407c ? reserved 0x01c8 4080 useraccess0 mdio user access register 0 0x01c8 4084 userphysel0 mdio user phy select register 0 0x01c8 4088 useraccess1 mdio user access register 1 0x01c8 408c userphysel1 mdio user phy select register 1 0x01c8 4090 - 0x01c8 47ff ? reserved submit documentation feedback peripheral information and electrical specifications 243
6.17.2 management data input/output (mdio) electrical data/timing 6.18 timers tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-74. timing requirements for mdio input (see figure 6-43 and figure 6-44 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t c(mdclk) cycle time, mdclk 400 ns 2 t w(mdclk) pulse duration, mdclk high/low 180 ns 3 t t(mdclk) transition time, mdclk 5 ns 4 t su(mdio-mdclkh) setup time, mdio data input valid before mdclk high 10 ns 5 t h(mdclkh-mdio) hold time, mdio data input valid after mdclk high 10 ns figure 6-43. mdio input timing table 6-75. switching characteristics over recommended operating conditions for mdio output (see figure 6-44 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 7 t d(mdclkl-mdio) delay time, mdclk low to mdio data output valid 100 ns figure 6-44. mdio output timing the dm6433 device has 3 64-bit general-purpose timers which have the following features: 64-bit count-up counter timer modes: ? 64-bit general-purpose timer mode (timer 0 and 1) ? dual 32-bit general-purpose timer mode (timer 0 and 1) ? watchdog timer mode (timer 2) 2 possible clock sources: peripheral information and electrical specifications 244 submit documentation feedback 1 4 5 mdclk mdio (input) 3 3 1 7 mdclk mdio (output)
6.18.1 timer peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 ? internal clock ? external clock input via timer input pin tinpl (timer 0 and 1 only) 2 operation modes: ? one-time operation (timer runs for one period then stops) ? continuous operation (timer automatically resets after each period) generates interrupts to the dsp generates sync event to edma causes device global reset upon watchdog timer timeout (timer 2 only) for more detailed information, see section 2.9 , documentation support for the tms320dm643x dmp 64-bit timer user's guide (literature number spru989). table 6-76. timer 0 registers hex address range acronym description 0x01c2 1400 - reserved 0x01c2 1404 emumgt_clkspd timer 0 emulation management/clock speed register 0x01c2 1410 tim12 timer 0 counter register 12 0x01c2 1414 tim34 timer 0 counter register 34 0x01c2 1418 prd12 timer 0 period register 12 0x01c2 141c prd34 timer 0 period register 34 0x01c2 1420 tcr timer 0 control register 0x01c2 1424 tgcr timer 0 global control register 0x01c2 1428 - 0x01c2 17ff - reserved table 6-77. timer 1 registers hex address range acronym description 0x01c2 1800 - reserved 0x01c2 1804 emumgt_clkspd timer 1 emulation management/clock speed register 0x01c2 1810 tim12 timer 1 counter register 12 0x01c2 1814 tim34 timer 1 counter register 34 0x01c2 1818 prd12 timer 1 period register 12 0x01c2 181c prd34 timer 1 period register 34 0x01c2 1820 tcr timer 1 control register 0x01c2 1824 tgcr timer 1 global control register 0x01c2 1828 - 0x01c2 1bff - reserved table 6-78. timer 2 (watchdog) registers hex address range acronym description 0x01c2 1c00 - reserved 0x01c2 1c04 emumgt_clkspd timer 2 emulation management/clock speed register 0x01c2 1c10 tim12 timer 2 counter register 12 0x01c2 1c14 tim34 timer 2 counter register 34 0x01c2 1c18 prd12 timer 2 period register 12 0x01c2 1c1c prd34 timer 2 period register 34 0x01c2 1c20 tcr timer 2 control register 0x01c2 1c24 tgcr timer 2 global control register 0x01c2 1c28 wdtcr timer 2 watchdog timer control register submit documentation feedback peripheral information and electrical specifications 245
6.18.2 timer electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-78. timer 2 (watchdog) registers (continued) hex address range acronym description 0x01c2 1c2c - 0x01c2 1fff - reserved table 6-79. timing requirements for timer input (1) (2) (3) (see figure 6-45 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max tinp0l, if timerctl.tinp0sel = 0 2p ns [default] 1 t w(tinph) pulse duration, tinpxl high tinp0l, if timerctl.tinp0sel = 1 0.33p ns tinp1l 2p ns tinp0l, if timerctl.tinp0sel = 0 2p ns [default] 2 t w(tinpl) pulse duration, tinpxl low tinp0l, if timerctl.tinp0sel = 1 0.33p ns tinp1l 2p ns (1) p = mxi/clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use p = 37.0 37 ns. (2) the timerctl.tinp0sel field in the system module determines if the tinp0l input directly goes to timer 0 (timerctl.tinp0sel=0), or if the tinp0l input is first divided down by 6 before going to timer 0 (timerctl.tinp0sel=1). (3) tinp1l input goes directly to timer 1. table 6-80. switching characteristics over recommended operating conditions for timer output (1) (see figure 6-45 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 3 t w(touth) pulse duration, toutxl high p ns 4 t w(toutl) pulse duration, toutxl low p ns (1) p = mxi/clkin cycle time in ns. for example, when mxi/clkin frequency is 27 mhz, use p = 37.0 37 ns. figure 6-45. timer timing 246 peripheral information and electrical specifications submit documentation feedback tinpxl toutxl 1 2 3 4
6.19 peripheral component interconnect (pci) 6.19.1 pci device-specific information tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the dm6433 dmp supports connections to pci-compliant devices via the integrated pci master/slave bus interface. the pci port interfaces to dsp internal resources via the data switched central resource. the data switched central resource is described in more detail in section 4 , system interconnect. for more detailed information on the pci port peripheral module, see the tms320dm643x dmp peripheral component interconnect (pci) user's guide (literature number spru985). the pci peripheral can act both as a pci bus master and as a target. it supports pci bus operation of speeds up to 33 mhz and uses a 32-bit data/address bus. on the dm6433 device, the pins of the pci peripheral are multiplexed with the pins of the vpss, emifa, gpio, hpi, vlynq, and emac peripherals. for more detailed information on how to select pci, see section 3 , device configurations. the dm6433 device provides an initialization mechanism through which the default values for some of the pci configuration registers can be read from an i2c eeprom. table 6-81 shows the registers which can be initialized through the pci auto-initialization. the default value of these registers when pci auto-initialization is not used is also shown in table 6-81 . pci auto-initialization is enabled by selecting pci boot with auto-initialization. for information on how to select pci boot with auto-initialization, see section 3.4.1 , boot modes. for more information on pci auto-initialization, see the tms320dm643x dmp peripheral component interconnect (pci) user's guide (literature number spru985 ) and the using the tms320dm643x bootloader application report (literature number spraag0 ). the pci peripheral is a master peripheral within the dm6433 dmp. table 6-81. default values for pci configuration registers register default value (hex) vendor id 104c device id b001 class code 11 8000 revision id 01 system vendor id 0000 subsystem id 0000 max latency 00 min grant 00 interrupt pin 00 interrupt line 00 submit documentation feedback peripheral information and electrical specifications 247
6.19.2 pci peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-82. pci memory-mapped registers dsp access acronym dsp access register name hex address range 01c1 a000 - 01c1 a00f - reserved 01c1 a010 pcistatset pci status set register 01c1 a014 pcistatclr pci status clear register 01c1 a018 - 01c1 a01f - reserved 01c1 a020 pcihintset pci host interrupt enable set register 01c1 a024 pcihintclr pci host interrupt enable clear register 01c1 a028 - 01c1 a02f - reserved 01c1 a030 pcidintset pci dsp interrupt enable set register 01c1 a034 pcidintclr pci dsp interrupt enable clear register 01c1 a038 - 01c1 a0ff - reserved 01c1 a100 pcivendevmir pci vendor id/device id mirror register 01c1 a104 pcicsrmir pci command/status mirror register 01c1 a108 pciclrevmir pci class code/revision id mirror register 01c1 a10c pciclinemir pci bist/header type/latency timer/cacheline size mirror register 01c1 a110 pcibar0msk pci base address mask register 0 01c1 a114 pcibar1msk pci base address mask register 1 01c1 a118 pcibar2msk pci base address mask register 2 01c1 a11c pcibar3msk pci base address mask register 3 01c1 a120 pcibar4msk pci base address mask register 4 01c1 a124 pcibar5msk pci base address mask register 5 01c1 a128 - 01c1 a12b - reserved 01c1 a12c pcisubidmir pci subsystem vendor id/subsystem id mirror register 01c1 a130 - reserved 01c1 a134 pcicpbptrmir pci capabilities pointer mirror register 01c1 a138 - 01c1 a13b - reserved 01c1 a13c pcilgintmir pci max latency/min grant/interrupt pin/interrupt line mirror register 01c1 a140 - 01c1 a17f - reserved 01c1 a180 pcislvcntl pci slave control register 01c1 a184 - 01c1 a1bf - reserved 01c1 a1c0 pcibar0trl pci slave base address 0 translation register 01c1 a1c4 pcibar1trl pci slave base address 1 translation register 01c1 a1c8 pcibar2trl pci slave base address 2 translation register 01c1 a1cc pcibar3trl pci slave base address 3 translation register 01c1 a1d0 pcibar4trl pci slave base address 4 translation register 01c1 a1d4 pcibar5trl pci slave base address 5 translation register 01c1 a1d8 - 01c1 a1df - reserved 01c1 a1e0 pcibar0mir pci base address register 0 mirror register 01c1 a1e4 pcibar1mir pci base address register 1 mirror register 01c1 a1e8 pcibar2mir pci base address register 2 mirror register 01c1 a1ec pcibar3mir pci base address register 3 mirror register 01c1 a1f0 pcibar4mir pci base address register 4 mirror register 01c1 a1f4 pcibar5mir pci base address register 5 mirror register 01c1 a1f8 - 01c1 a2ff - reserved 01c1 a300 pcimcfgdat pci master configuration/io access data register peripheral information and electrical specifications 248 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-82. pci memory-mapped registers (continued) dsp access acronym dsp access register name hex address range 01c1 a304 pcimcfgadr pci master configuration/io access address register 01c1 a308 pcimcfgcmd pci master configuration/io access command register 01c1 a30c - 01c1 a30f - reserved 01c1 a310 pcimstcfg pci master configuration register 01c1 a314 pciaddsub0 pci address substitution 0 register 01c1 a318 pciaddsub1 pci address substitution 1 register 01c1 a31c pciaddsub2 pci address substitution 2 register 01c1 a320 pciaddsub3 pci address substitution 3 register 01c1 a324 pciaddsub4 pci address substitution 4 register 01c1 a328 pciaddsub5 pci address substitution 5 register 01c1 a32c pciaddsub6 pci address substitution 6 register 01c1 a330 pciaddsub7 pci address substitution 7 register 01c1 a334 pciaddsub8 pci address substitution 8 register 01c1 a338 pciaddsub9 pci address substitution 9 register 01c1 a33c pciaddsub10 pci address substitution 10 register 01c1 a340 pciaddsub11 pci address substitution 11 register 01c1 a344 pciaddsub12 pci address substitution 12 register 01c1 a348 pciaddsub13 pci address substitution 13 register 01c1 a34c pciaddsub14 pci address substitution 14 register 01c1 a350 pciaddsub15 pci address substitution 15 register 01c1 a354 pciaddsub16 pci address substitution 16 register 01c1 a358 pciaddsub17 pci address substitution 17 register 01c1 a35c pciaddsub18 pci address substitution 18 register 01c1 a360 pciaddsub19 pci address substitution 19 register 01c1 a364 pciaddsub20 pci address substitution 20 register 01c1 a368 pciaddsub21 pci address substitution 21 register 01c1 a36c pciaddsub22 pci address substitution 22 register 01c1 a370 pciaddsub23 pci address substitution 23 register 01c1 a374 pciaddsub24 pci address substitution 24 register 01c1 a378 pciaddsub25 pci address substitution 25 register 01c1 a37c pciaddsub26 pci address substitution 26 register 01c1 a380 pciaddsub27 pci address substitution 27 register 01c1 a384 pciaddsub28 pci address substitution 28 register 01c1 a388 pciaddsub29 pci address substitution 29 register 01c1 a38c pciaddsub30 pci address substitution 30 register 01c1 a390 pciaddsub31 pci address substitution 31 register submit documentation feedback peripheral information and electrical specifications 249
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-83. pci hook configuration registers dsp access acronym dsp access register name hex address range 01c1 a394 pcivendevprg pci vendor id and device id program register 01c1 a398 ? reserved 01c1 a39c pciclrevprg pci class code and revision id program register 01c1 a3a0 pcisubidprg pci subsystem vendor id and subsystem id program register 01c1 a3a4 pcimaxlgprg pci max latency and min grant program register 01c1 a3a8 ? reserved 01c1 a3ac pcicfgdone pci configuration done register 01c1 a3b0 - 01c1 a7ff ? reserved peripheral information and electrical specifications 250 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-84. pci external memory space hex address range acronym pci master window 3000 0000 - 307f ffff - pci master window 0 3080 0000 - 30ff ffff - pci master window 1 3100 0000 - 317f ffff - pci master window 2 3180 0000 - 31ff ffff - pci master window 3 3200 0000 - 327f ffff - pci master window 4 3280 0000 - 32ff ffff - pci master window 5 3300 0000 - 337f ffff - pci master window 6 3380 0000 - 33ff ffff - pci master window 7 3400 0000 - 347f ffff - pci master window 8 3480 0000 - 34ff ffff - pci master window 9 3500 0000 - 357f ffff - pci master window 10 3580 0000 - 35ff ffff - pci master window 11 3600 0000 - 367f ffff - pci master window 12 3680 0000 - 36ff ffff - pci master window 13 3700 0000 - 377f ffff - pci master window 14 3780 0000 - 37ff ffff - pci master window 15 3800 0000 - 387f ffff - pci master window 16 3880 0000 - 38ff ffff - pci master window 17 3900 0000 - 397f ffff - pci master window 18 3980 0000 - 39ff ffff - pci master window 19 3a00 0000 - 3a7f ffff - pci master window 20 3a80 0000 - 3aff ffff - pci master window 21 3b00 0000 - 3b7f ffff - pci master window 22 3b80 0000 - 3bff ffff - pci master window 23 3c00 0000 - 3c7f ffff - pci master window 24 3c80 0000 - 3cff ffff - pci master window 25 3d00 0000 - 3d7f ffff - pci master window 26 3d80 0000 - 3dff ffff - pci master window 27 3e00 0000 - 3e7f ffff - pci master window 28 3e80 0000 - 3eff ffff - pci master window 29 3f00 0000 - 3f7f ffff - pci master window 30 3f80 0000 - 3fff ffff - pci master window 31 submit documentation feedback peripheral information and electrical specifications 251
6.19.3 pci electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com texas instruments (ti) has performed the simulation and system characterization to ensure that the pci peripheral meets all ac timing specifications as required by the pci local bus specification revision 2.3. therefore, the ac timing specifications are not reproduced here. for more information on the ac timing specifications, see section 4.2.3, timing specification (33-mhz timing) of the pci local bus specification revision 2.3. note: the dm6433 pci peripheral only supports 3.3-v signaling and 33-mhz operation. 252 peripheral information and electrical specifications submit documentation feedback
6.20 pulse width modulator (pwm) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the 3 dm6433 pulse width modulator (pwm) peripherals support the following features: period counter first-phase duration counter repeat count for one-shot operation configurable to operate in either one-shot or continuous mode buffered period and first-phase duration registers one-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low). one-shot operation generates n+1 periods of waveform, n being the repeat count register value emulation support the register memory maps for pwm0/1/2 are shown in table 6-85 , table 6-86 , and table 6-87 . table 6-85. pwm0 register memory map hex address range acronym register name 0x01c2 2000 reserved 0x01c2 2004 pcr pwm0 peripheral control register 0x01c2 2008 cfg pwm0 configuration register 0x01c2 200c start pwm0 start register 0x01c2 2010 rpt pwm0 repeat count register 0x01c2 2014 per pwm0 period register 0x01c2 2018 ph1d pwm0 first-phase duration register 0x01c2 201c - 0x01c2 23ff - reserved table 6-86. pwm1 register memory map hex address range acronym register name 0x01c2 2400 reserved 0x01c2 2404 pcr pwm1 peripheral control register 0x01c2 2408 cfg pwm1 configuration register 0x01c2 240c start pwm1 start register 0x01c2 2410 rpt pwm1 repeat count register 0x01c2 2414 per pwm1 period register 0x01c2 2418 ph1d pwm1 first-phase duration register 0x01c2 241c -0x01c2 27ff - reserved table 6-87. pwm2 register memory map hex address range acronym register name 0x01c2 2800 reserved 0x01c2 2804 pcr pwm2 peripheral control register 0x01c2 2808 cfg pwm2 configuration register 0x01c2 280c start pwm2 start register 0x01c2 2810 rpt pwm2 repeat count register 0x01c2 2814 per pwm2 period register 0x01c2 2818 ph1d pwm2 first-phase duration register 0x01c2 281c - 0x01c2 2bff - reserved submit documentation feedback peripheral information and electrical specifications 253
6.20.1 pwm0/1/2 electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-88. switching characteristics over recommended operating conditions for pwm0/1/2 outputs (see figure 6-46 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 1 t w(pwmh) pulse duration, pwmx high 37 ns 2 t w(pwml) pulse duration, pwmx low 37 ns 3 t t(pwm) transition time, pwmx 5 ns figure 6-46. pwm output timing 254 peripheral information and electrical specifications submit documentation feedback pwm0/1/2 1 3 3 2
6.21 vlynq 6.21.1 vlynq peripheral register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the dm6433 vlynq peripheral provides a high speed serial communications interface with the following features. low pin count scalable performance / support simple packet based transfer protocol for memory mapped access ? write request / data packet ? read request packet ? read response data packet ? interrupt request packet supports both symmetric and asymmetric operation ? tx pins on first device connect to rx pins on second device and vice versa ? data pin widths are automatically detected after reset ? request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins ? supports both host/peripheral and peer to peer communication simple block code packet formatting (8b/10b) in band flow control ? no extra pins needed ? allows receiver to momentarily throttle back transmitter when overflow is about to occur ? uses built in special code capability of block code to seamlessly interleave flow control information with user data ? allows system designer to balance cost of data buffering versus performance multiple outstanding transactions automatic packet formatting optimizations internal loop-back mode table 6-89. vlynq registers hex address range acronym register name 0x01e0 1000 - reserved 0x01e0 1004 ctrl vlynq local control register 0x01e0 1008 stat vlynq local status register 0x01e0 100c intpri vlynq local interrupt priority vector status/clear register 0x01e0 1010 intstatclr vlynq local unmasked interrupt status/clear register 0x01e0 1014 intpendset vlynq local interrupt pending/set register 0x01e0 1018 intptr vlynq local interrupt pointer register 0x01e0 101c xam vlynq local transmit address map register 0x01e0 1020 rams1 vlynq local receive address map size 1 register 0x01e0 1024 ramo1 vlynq local receive address map offset 1 register 0x01e0 1028 rams2 vlynq local receive address map size 2 register 0x01e0 102c ramo2 vlynq local receive address map offset 2 register 0x01e0 1030 rams3 vlynq local receive address map size 3 register 0x01e0 1034 ramo3 vlynq local receive address map offset 3 register 0x01e0 1038 rams4 vlynq local receive address map size 4 register 0x01e0 103c ramo4 vlynq local receive address map offset 4 register submit documentation feedback peripheral information and electrical specifications 255
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-89. vlynq registers (continued) hex address range acronym register name 0x01e0 1040 chipver vlynq local chip version register 0x01e0 1044 autngo vlynq local auto negotiation register 0x01e0 1048 - reserved 0x01e0 104c - reserved 0x01e0 1050 - 0x01e0 105c - reserved 0x01e0 1060 - reserved 01e0 10c00 0064 - reserved 0x01e0 1068 - 0x01e0 107c - reserved for future use 0x01e0 1080 rrevid vlynq remote revision register 0x01e0 1084 rctrl vlynq remote control register 0x01e0 1088 rstat vlynq remote status register 0x01e0 108c rintpri vlynq remote interrupt priority vector status/clear register 0x01e0 1090 rintstatclr vlynq remote unmasked interrupt status/clear register 0x01e0 1094 rintpendset vlynq remote interrupt pending/set register 0x01e0 1098 rintptr vlynq remote interrupt pointer register 0x01e0 109c rxam vlynq remote transmit address map register 0x01e0 10a0 rrams1 vlynq remote receive address map size 1 register 0x01e0 10a4 rramo1 vlynq remote receive address map offset 1 register 0x01e0 10a8 rrams2 vlynq remote receive address map size 2 register 0x01e0 10ac rramo2 vlynq remote receive address map offset 2 register 0x01e0 10b0 rrams3 vlynq remote receive address map size 3 register 0x01e0 10b4 rramo3 vlynq remote receive address map offset 3 register 0x01e0 10b8 rrams4 vlynq remote receive address map size 4 register 0x01e0 10bc rramo4 vlynq remote receive address map offset 4 register vlynq remote chip version register (values on the device_id and 0x01e0 10c0 rchipver device_rev pins of remote vlynq) 0x01e0 10c4 rautngo vlynq remote auto negotiation register 0x01e0 10c8 rmanngo vlynq remote manual negotiation register 0x01e0 10cc rngostat vlynq remote negotiation status register 0x01e0 10d0 - 0x01e0 10dc - reserved vlynq remote interrupt vectors 3 - 0 (sourced from vlynq_int_i[3:0] port of 0x01e0 10e0 rintvec0 remote vlynq) vlynq remote interrupt vectors 7 - 4 (sourced from vlynq_int_i[7:4] port of 0x01e0 10e4 rintvec1 remote vlynq) 0x01e0 10e8 - 0x01e0 10fc - reserved for future use 0x01e0 1100 - 0x01e0 1fff - reserved peripheral information and electrical specifications 256 submit documentation feedback
6.21.2 vlynq electrical data/timing tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-90. timing requirements for vlynq_clk input (see figure 6-47 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t c(vclk) cycle time, vlynq_clk 10 ns 2 t w(vclkh) pulse duration, vlynq_clk high 3 ns 3 t w(vclkl) pulse duration, vlynq_clk low 3 ns table 6-91. switching characteristics over recommended operating conditions for vlynq_clk output (see figure 6-47 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 1 t c(vclk) cycle time, vlynq_clk 10 ns 2 t w(vclkh) pulse duration, vlynq_clk high 4 ns 3 t w(vclkl) pulse duration, vlynq_clk low 4 ns figure 6-47. vlynq_clk timing for vlynq table 6-92. switching characteristics over recommended operating conditions for transmit data for the vlynq module (see figure 6-48 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max t d(vclkh- 1 delay time, vlynq_clk high to vlynq_txd[3:0] invalid 2.25 ns txdi) t d(vclkh- 2 delay time, vlynq_clk high to vlynq_txd[3:0] valid 12 ns txdv) submit documentation feedback peripheral information and electrical specifications 257 vlynq_clk 3 1 2
tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-93. timing requirements for receive data for the vlynq module (1) (see figure 6-48 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max rtm disabled, rtm sample = 3 1.75 ns setup time, vlynq_rxd[3:0] valid before 3 t su(rxdv-vclkh) vlynq_clk high rtm enabled (1) ns rtm disabled, rtm sample = 3 3 ns hold time, vlynq_rxd[3:0] valid after 4 t h(vclkh-rxdv) vlynq_clk high rtm enabled (1) ns (1) the vlynq receive timing manager (rtm) is a serial receive logic designed to eliminate setup and hold violations that could occur in traditional input signals. rtm logic automatically selects the setup and hold timing from one of eight data flops (see table 6-94 ). when rtm logic is disabled, the setup and hold timing from the default data flop (3) is used. table 6-94. rtm rx data flop hold/setup timing constraints (typical values) rx data flop hold (y) setup (x) 0 1.3 0.9 1 1.4 0.7 2 1.5 -0.4 3 1.6 -0.6 4 1.8 -0.8 5 2.0 -1.0 6 2.2 -1.1 7 2.4 -1.2 figure 6-48. vlynq transmit/receive timing 258 peripheral information and electrical specifications submit documentation feedback vlynq_clk vlynq_txd[3:0] vlynq_rxd[3:0] 1 2 3 4 datadata
6.22 general-purpose input/output (gpio) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the gpio peripheral provides general-purpose pins that can be configured as either inputs or outputs. when configured as an output, a write to an internal register can control the state driven on the output pin. when configured as an input, the state of the input is detectable by reading the state of an internal register. in addition, the gpio peripheral can produce cpu interrupts and edma events in different interrupt/event generation modes. the gpio peripheral provides generic connections to external devices. the gpio pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of gp[0:15]). the dm6433 gpio peripheral supports the following: up to 111 3.3-v gpio pins, gp[0:110] interrupts: ? up to 8 unique gp[0:7] interrupts from bank 0 ? 7 gpio bank (aggregated) interrupt signals from each of the 7 banks of gpios ? interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable gpio signal dma events: ? up to 8 unique gpio dma events from bank 0 ? 7 gpio bank (aggregated) dma event signals from each of the 7 banks of gpios set/clear functionality: firmware writes 1 to corresponding bit position(s) to set or to clear gpio signal(s). this allows multiple firmware processes to toggle gpio output signals without critical section protection (disable interrupts, program gpio, re-enable interrupts, to prevent context switching to anther process during gpio programming). separate input/output registers output register in addition to set/clear so that, if preferred by firmware, some gpio output signals can be toggled by direct write to the output register(s). output register, when read, reflects output drive status. this, in addition to the input register reflecting pin status and open-drain i/o cell, allows wired logic be implemented. the memory map for the gpio registers is shown in table 6-95 . for more detailed information on gpios, see the tms320dm643x dmp general-purpose input/output (gpio) user's guide (literature number spru988 ). submit documentation feedback peripheral information and electrical specifications 259
6.22.1 gpio peripheral register description(s) tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-95. gpio registers hex address range acronym register name 0x01c6 7000 pid peripheral identification register 0x01c6 7004 - reserved 0x01c6 7008 binten gpio interrupt per-bank enable gpio banks 0 and 1 0x01c6 700c - reserved 0x01c6 7010 dir01 gpio banks 0 and 1 direction register (gp[0:31]) 0x01c6 7014 out_data01 gpio banks 0 and 1 output data register (gp[0:31]) 0x01c6 7018 set_data01 gpio banks 0 and 1 set data register (gp[0:31]) 0x01c6 701c clr_data01 gpio banks 0 and 1 clear data for banks 0 and 1 (gp[0:31]) 0x01c6 7020 in_data01 gpio banks 0 and 1 input data register (gp[0:31]) 0x01c6 7024 set_ris_trig01 gpio banks 0 and 1 set rising edge interrupt register (gp[0:31]) 0x01c6 7028 clr_ris_trig01 gpio banks 0 and 1 clear rising edge interrupt register (gp[0:31]) 0x01c6 702c set_fal_trig01 gpio banks 0 and 1 set falling edge interrupt register (gp[0:31]) 0x01c6 7030 clr_fal_trig01 gpio banks 0 and 1 clear falling edge interrupt register (gp[0:31]) 0x01c6 7034 instat01 gpio banks 0 and 1 interrupt status register (gp[0:31]) gpio banks 2 and 3 0x01c6 7038 dir23 gpio banks 2 and 3 direction register (gp[32:63]) 0x01c6 703c out_data23 gpio banks 2 and 3 output data register (gp[32:63]) 0x01c6 7040 set_data23 gpio banks 2 and 3 set data register (gp[32:63]) 0x01c6 7044 clr_data23 gpio banks 2 and 3 clear data register (gp[32:63]) 0x01c6 7048 in_data23 gpio banks 2 and 3 input data register (gp[32:63]) 0x01c6 704c set_ris_trig23 gpio banks 2 and 3 set rising edge interrupt register (gp[32:63]) 0x01c6 7050 clr_ris_trig23 gpio banks 2 and 3 clear rising edge interrupt register (gp[32:63]) 0x01c6 7054 set_fal_trig23 gpio banks 2 and 3 set falling edge interrupt register (gp[32:63]) 0x01c6 7058 clr_fal_trig23 gpio banks 2 and 3 clear falling edge interrupt register (gp[32:63]) 0x01c6 705c instat23 gpio banks 2 and 3 interrupt status register (gp[32:63]) gpio bank 4 and 5 0x01c6 7060 dir45 gpio bank 4 and 5 direction register (gp[64:95]) 0x01c6 7064 out_data45 gpio bank 4 and 5 output data register (gp[64:95]) 0x01c6 7068 set_data45 gpio bank 4 and 5 set data register (gp[64:95]) 0x01c6 706c clr_data45 gpio bank 4 and 5 clear data register (gp[64:95]) 0x01c6 7070 in_data45 gpio bank 4 and 5 input data register (gp[64:95]) 0x01c6 7074 set_ris_trig45 gpio bank 4 and 5 set rising edge interrupt register (gp[64:95]) 0x01c6 7078 clr_ris_trig45 gpio bank 4 and 5 clear rising edge interrupt register (gp[64:95]) 0x01c6 707c set_fal_trig45 gpio bank 4 and 5 set falling edge interrupt register (gp[64:95]) 0x01c6 7080 clr_fal_trig45 gpio bank 4 and 5 clear falling edge interrupt register (gp[64:95]) 0x01c6 7084 instat45 gpio bank 4 and 5 interrupt status register (gp[64:95]) gpio bank 6 0x01c6 7088 dir6 gpio bank 6 direction register (gp[96:110]) 0x01c6 708c out_data6 gpio bank 6 output data register (gp[96:110]) 0x01c6 7090 set_data6 gpio bank 6 set data register (gp[96:110]) 0x01c6 7094 clr_data6 gpio bank 6 clear data register (gp[96:110]) 0x01c6 7098 in_data6 gpio bank 6 input data register (gp[96:110]) 0x01c6 709c set_ris_trig6 gpio bank 6 set rising edge interrupt register (gp[96:110]) 0x01c6 70a0 clr_ris_trig6 gpio bank 6 clear rising edge interrupt register (gp[96:110]) peripheral information and electrical specifications 260 submit documentation feedback
tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 table 6-95. gpio registers (continued) hex address range acronym register name 0x01c6 70a4 set_fal_trig6 gpio bank 6 set falling edge interrupt register (gp[96:110]) 0x01c6 70a8 clr_fal_trig6 gpio bank 6 clear falling edge interrupt register (gp[96:110]) 0x01c6 70ac instat6 gpio bank 6 interrupt status register (gp[96:110]) 0x01c6 70b0 - 0x01c6 7fff - reserved submit documentation feedback peripheral information and electrical specifications 261
6.22.2 gpio peripheral input/output electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-96. timing requirements for gpio inputs (1) (see figure 6-49 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t w(gpih) pulse duration, gp[x] input high 2c (2) ns 2 t w(gpil) pulse duration, gp[x] input low 2c (2) ns (1) the pulse width given is sufficient to generate a cpu interrupt or an edma event. however, if a user wants to have dm6433 recognize the gp[x] input changes through software polling of the gpio register, the gp[x] input duration must be extended to allow dm6433 enough time to access the gpio register through the internal bus. (2) c = sysclk3 period in ns. for example, when running parts at 600 mhz, use c = 10ns. table 6-97. switching characteristics over recommended operating conditions for gpio outputs (see figure 6-49 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 3 t w(gpoh) pulse duration, gp[x] output high 2c (1) (2) ns 4 t w(gpol) pulse duration, gp[x] output low 2c (1) (2) ns (1) this parameter value should not be used as a maximum performance specification. actual performance of back-to-back accesses of the gpio is dependent upon internal bus activity. (2) c = sysclk3 period in ns. for example, when running parts at 600 mhz, use c = 10ns. figure 6-49. gpio port timing 262 peripheral information and electrical specifications submit documentation feedback gp[x] input gp[x] output 4 3 2 1
6.23 ieee 1149.1 jtag 6.23.1 jtag id (jtagid) register description(s) tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the jtag (3) interface is used for bsdl testing and emulation of the dm6433 device. trst only needs to be released when it is necessary to use a jtag controller to debug the device or exercise the device's boundary scan functionality. note: trst is synchronous and must be clocked by tck; otherwise, the boundary scan logic may not respond as expected after trst is asserted. for maximum reliability, dm6433 includes an internal pulldown (ipd) on the trst pin to ensure that trst will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. jtag controllers from texas instruments actively drive trst high. however, some third-party jtag controllers may not drive trst high but expect the use of a pullup resistor on trst. when using this type of jtag controller, assert trst to initialize the device after powerup and externally drive trst high before attempting any emulation or boundary scan operations. (3) ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. table 6-98. jtag id (jtagid) register hex address range acronym register name comments read-only. provides 32-bit 0x01c4 0028 jtagid jtag identification register jtag id of the device. the jtag id register is a read-only register that identifies to the customer the jtag/device id. for the dm6433 device, the jtag id register resides at address location 0x01c4 0028. for the actual register bit names and their associated bit field descriptions, see figure 6-50 and table 6-99 . 31-28 27-12 11-1 0 variant (4-bit) part number (16-bit) manufacturer (11-bit) lsb r-n r-1011 0111 0010 0001 r-0000 0010 111 r-1 legend: r = read, w = write, n = value at reset figure 6-50. jtag id (jtagid) register?0x01c4 0028 table 6-99. jtag id (jtagid) register selection bit descriptions bit name description 31:28 variant variant (4-bit) value. a read from this field always returns 0b0000. 27:12 part number part number (16-bit) value. dm6433 value: 1011 0111 0010 0001. 11-1 manufacturer manufacturer (11-bit) value. dm6433 value: 0000 0010 111. 0 lsb lsb. this bit is read as a "1" for dm6433. submit documentation feedback peripheral information and electrical specifications 263
6.23.2 jtag electrical data/timing tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 6-100. timing requirements for jtag test port (see figure 6-51 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. unit min max 1 t c(tck) cycle time, tck 33 ns 3 t su(tdiv-tckh) setup time, tdi/tms/ trst valid before tck high 2.5 ns 4 t h(tckh-tdiv) hold time, tdi/tms/ trst valid after tck high 16.5 ns table 6-101. switching characteristics over recommended operating conditions for jtag test port (see figure 6-51 ) -7/-6/-5/-4 -l/-q6/-q5/-q4 no. parameter unit min max 2 t d(tckl-tdov) delay time, tck low to tdo valid 0 14 ns figure 6-51. jtag test-port timing peripheral information and electrical specifications 264 submit documentation feedback tck tdo tdi/tms/trst 1 2 3 4 2
7 mechanical data 7.1 thermal data for zwt tms320dm6433 digital media processor www.ti.com sprs343c ? november 2006 ? revised june 2008 the following table(s) show the thermal resistance characteristics for the pbga?zwt and zdu mechanical package(s). for more details, see the thermal considerations for tms320dm64xx, tms320dm64x, and tms320c6000 devices application report (literature number spraal9 ). table 7-1. thermal resistance characteristics (pbga package) [zwt] no. c/w (1) air flow (m/s) (2) 1 r integrated circuits thermal test method environment conditions - natural convection (still air) eia/jesd51-3, low effective thermal conductivity test board for leaded surface mount packages jesd51-7, high effective thermal conductivity test board for leaded surface mount packages . (2) m/s = meters per second submit documentation feedback mechanical data 265
7.1.1 thermal data for zdu 7.1.2 packaging information tms320dm6433 digital media processor sprs343c ? november 2006 ? revised june 2008 www.ti.com table 7-2. thermal resistance characteristics (pbga package) [zdu] no. c/w (1) air flow (m/s) (2) 1 r integrated circuits thermal test method environment conditions - natural convection (still air) eia/jesd51-3, low effective thermal conductivity test board for leaded surface mount packages jesd51-7, high effective thermal conductivity test board for leaded surface mount packages (2) m/s = meters per second the following packaging information and addendum reflect the most current data available for the designated device(s). this data is subject to change without notice and without revision of this document. 266 mechanical data submit documentation feedback
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tms320dm6433zdu4 nrnd bga zdu 376 green (rohs & no sb/br) snagcu level-3-260c-168 hr l2 dm6433zdu tms320 4 tms320dm6433zdu6 nrnd bga zdu 376 60 green (rohs & no sb/br) snagcu level-3-260c-168 hr 0 to 90 dm6433zdu6 tms320dm6433zdu7 nrnd bga zdu 376 60 green (rohs & no sb/br) snagcu level-3-260c-168 hr l2 dm6433zdu tms320 7 tms320dm6433zwt4 nrnd nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr 0 to 90 l2 dm6433zwt tms320 4 tms320dm6433zwt5 nrnd nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr 0 to 90 l2 dm6433zwt tms320 5 tms320dm6433zwt6 nrnd nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr 0 to 90 l2 dm6433zwt tms320 tms320dm6433zwt7 nrnd nfbga zwt 361 90 pb-free (rohs) snagcu level-3-260c-168 hr l2 dm6433zwt tms320 7 tms320dm6433zwtl nrnd nfbga zwt 361 pb-free (rohs) snagcu level-3-260c-168 hr l2 dm6433zwtl tms320 tms320dm6433zwtq5 active nfbga zwt 361 pb-free (rohs) snagcu level-3-260c-168 hr -40 to 125 l1 dm6433zwtq tms320 5 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

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